In interlaced mode, the vertical total lines for frames 0 and 1 may not
necessarily be equal (off by 1). The pixel clock calculation needs to take this
into account by taking their average.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This function checks if a video timing with a supplied ID from the video mode
table is interlaced or not.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Removed 25 Hz and 30 Hz refresh rates since they have identical video timings to
the 50 Hz and 60 Hz varients. The 50/60Hz refresh rates take into account both
frames for interlaced.
The common video functions use the 50/60Hz refresh rates and divide by 2 where
needed to get the frame rate for each frame.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
For compliance, training pattern 0 should be written without using a burst write
for voltage swing and pre-emphasis values.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
For compliance purposes, training pattern 0 needs to be sent between
downshifting of lane count and link rates.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Since the RX handler initialization functions assert that the core is of type
RX, the configuration initialization function must be called prior to the
handlers being set.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Functions now assert the core context upon which they operate.
XDp_Tx* functions are meant to be used with the DisplayPort core in the TX mode
of operation.
XDp_Rx* functions are meant to be used with the DisplayPort core in the RX mode
of operation.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Rather than on the configuration structure pointer.
This makes it cleaner and easier to use as this function is an API function.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
XDp is used as an argument for all API functions. If a user application uses a
deprecated structure, it is automatically converted to the top-level XDp
structure which contains either a XDp_Tx or XDp_Rx structure which corresponds
to the previous XDptx and XDprx.
This is done for back-wards compatability with the dptx driver to minimize user
effort in migrating to the new dp driver.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
If link does not need to be re-enabled, then it is already disabled. Don't need
to disable the link again.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
If the DisplayPort core is configured for 1 or 2 maximum lanes, wait for PHY to
be ready only on those lanes rather than waiting on all 4 lanes.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Lines should not exceed 80 characters in length.
The pre-processor only replaces full names, so prefixes cannot be altered using
macros (#define XDPTX_ XDP_TX_).
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Added frame rate into DisplayPort calculations to follow updates for the
commone video driver.
Note, this is the deprecated TX-only driver for DisplayPort (the TX-only driver,
dptx, and the unified TX-RX driver, dp, are both released for 2015.1).
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
