Modify clock config function to move all ZynqMP GEM related code inside
XPAR_<psu ethernet ip> checks. This fixes the compilation errors for Zynq
that are caused by references to GEM2/3.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Corrected VsyncStart and also corrected register
read to XVTC_DVSYNC_F1_OFFSET in XVtc_GetDetector API
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Write to CRL_APB registers for clock control and enable 1G speed.
Move clock configuration to a separate function.
Update payload to jumbo size.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Read the phy idetifier register to identify whether PHY is Marvell or TI.
Add support for TI PHY sequence by writing to PHY CNTRL register and
tuning using RGMIICTL/RGMIIDCTL registers.
Access to extended registers in TI pHY is through REGCR and ADDAR registers.
ADDAR should be used to write the offset of register to be written
and then the value to be written. REGCR should indicate when ADDAR contains
register offset and when it contains register data.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Silicon 1.0 does not support switching to 1.8V and UHS mode.
Comment this code with a "broken" quirk.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
VTC in example design has switched to a slower 9MHz clock.This
essentially provides < 2fps frame rate. Vidout needs 3-4 frames
to acquire lock. After vpss configuration wait for 2 sec (mb_sleep)
before checking for vidout lock
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
v_tpg IP has a new example design available in vivado catalogue.
Associated example software is added to the driver along with
the xsct script to create sdk project
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
v_tpg example design uses enum definitions from video common
driver. Added dependency clause to include the video common
driver when tpg driver is sourced
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Vivado Example design tool flow change resulted in hdf file name
change of video processing subsystem example design. Update the
script to accept hdf file name from command line to avoid any
dependency on further name changes
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies driver tcl to show proper error message when
unsupported combination of IP and processor instance tries to
generate BSP e.g. if psu_rcpu_gic is not supported with cortex a53
and psu_acpu_gic is not supported with cortex r5
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Updated the system.c to use canonical name for MIG to avoid
dependency on instance name
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
xsct scipt file added to automate the process of generating the
elf file(s) from the provided hdf file
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This patch updates the iomodule to handle, if external interrupts
are not enabled.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
Update copyright year in source files and examples.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
This patch corrects the hsize and stride alignment logic when DRE
is not enabled in the design.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
- Added dynamic scaler filter selection logic
- Added indirection layer for sub-core API's (picture settings,
PIP background color, debug information)
- Fixed VDMA alignment in 1/2/4 pixel configurations
- Added example directory. Included files to be uused with
vpss example design that will be released separately
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
There are 4 filter coefficient tables available. The table to be
loaded in IP register bank is determined by the scaling ratio
Scale Up: Always use 6tap
Scale Dn: Different table selected based on scaling ratio
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
There are 4 Filter coefficient tables available. The table to be
loaded in the IP is determined by the scaling ratio
Scale Up: Always use 6tap
Scale Dn: Different table selected based on scaling ration
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Updated API name to load external coefficients to align with
vprocss
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Updated API name to load external coefficients to align with
vprocss update.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Modify example to use the first available IPI device slot
for testing
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
When DRE is not enabled,adjust hsize and stride to memap data width on write channel(S2MM).
On read channel(mm2s), adjust hsize to stream data width and stride to memap data width.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
