This patch fixes the wrong ifdef in the example.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
This patch updates the Xil_SetTlbAttributes
to mark the BD memory region only uncaheable and
updated the cache flush/invalidate api's for a53 case.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
In a53 processor the Cache flush api does both fulsh and invalidate
of the memory once the dma transfer is done before checking the
data we shouldn't invalidate the memory unlike the a9/microblaze case
this patch updates the axicdma examples for the same.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch updates the driver to support 64-bit addressing.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
