VTC in example design has switched to a slower 9MHz clock.This
essentially provides < 2fps frame rate. Vidout needs 3-4 frames
to acquire lock. After vpss configuration wait for 2 sec (mb_sleep)
before checking for vidout lock
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Vivado Example design tool flow change resulted in hdf file name
change of video processing subsystem example design. Update the
script to accept hdf file name from command line to avoid any
dependency on further name changes
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Updated the system.c to use canonical name for MIG to avoid
dependency on instance name
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
xsct scipt file added to automate the process of generating the
elf file(s) from the provided hdf file
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
- Added dynamic scaler filter selection logic
- Added indirection layer for sub-core API's (picture settings,
PIP background color, debug information)
- Fixed VDMA alignment in 1/2/4 pixel configurations
- Added example directory. Included files to be uused with
vpss example design that will be released separately
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
