embeddedsw/XilinxProcessorIPLib/drivers/vprocss/examples
Rohit Consul cf3ea2ed03 vprocss: Add 2 sec wait to example design source files
VTC in example design has switched to a slower 9MHz clock.This
essentially provides < 2fps frame rate. Vidout needs 3-4 frames
to acquire lock. After vpss configuration wait for 2 sec (mb_sleep)
before checking for vidout lock

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-09-15 18:47:40 +05:30
..
src vprocss: Add 2 sec wait to example design source files 2015-09-15 18:47:40 +05:30
readme.txt vprocss: Update example tcl to accept command line parameter 2015-09-04 23:23:29 +05:30
vpss_example.tcl vprocss: Update example tcl to accept command line parameter 2015-09-04 23:23:29 +05:30

vpss_example.tcl automates the process of generating the downloadable bit & elf files from the provided vpss example hdf file.

Example application design source files (contained within "examples/src" folder) are tightly coupled with the video processing subsystem example design available in Vivado Catalogue.
To run the provided tcl
  1. Copy the exported example design hdf file in the "examples" directory of the driver
  2. Launch the xsct terminal
  3. cd into the examples directory
  4. source the tcl file
		xsct%>source vpss_example.tcl
  4. execute the script
		xsct%>vpss_example <hdf_file_name.hdf>

Script will perform following operations
  1. Create workspace
  2. Create HW project
  3. Create BSP
  4. Create Application Project
  5. Build BSP and Application Project

After the process is complete required files will be available in
  bit file -> vpss_example.sdk/vpss_example_hw_platform folder
  elf file -> vpss_example.sdk/vpss_example_design/{Debug/Release} folder

When executed on the board the example application will determine the video processing subsystem topology and set the input and output stream configuration accordingly. Test pattern generator IP is used to generate the input stream. Video Lock Monitor IP will then monitor the output of the subsystem (to vidout) to determine if lock is achieved and present the status (Pass/Fail) on the terminal

Note: Serial terminal baud rate should be set to 9600