Xilinx Embedded Software (embeddedsw) Development

Jyotheeswar Reddy 4350a1fa00 sw_apps:zynqmp_pmufw: Clear IPI0 status register during core init ... swbeta2 commit 1b173007d1cc009bffeb2969a5a5bacc533647db IPI0 is used by PMUFW for PM requests and the mask is used for determining the Master. There are chances of IPIs being triggered before FW Init but un-handled or even bits that are not cleared by ROM, causing a corruption of the ISR mask. So PMUFW should cleanup these bits during startup Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>		2015-04-24 11:57:10 +05:30
doc	Change Log for 2015.1	2015-03-01 09:56:03 +05:30
lib	sw_apps:zynqmp_pmufw: Clear IPI0 status register during core init	2015-04-24 11:57:10 +05:30
ThirdParty/sw_services/xilopenamp	sw_services: openamp: change in makefile	2015-03-31 12:03:29 +05:30
XilinxProcessorIPLib/drivers	gpiops_v3_1 : Convert 3-line comments to 1-liners.	2015-04-22 11:48:33 +05:30