embeddedsw/XilinxProcessorIPLib/drivers/vprocss
Rohit Consul cf3ea2ed03 vprocss: Add 2 sec wait to example design source files
VTC in example design has switched to a slower 9MHz clock.This
essentially provides < 2fps frame rate. Vidout needs 3-4 frames
to acquire lock. After vpss configuration wait for 2 sec (mb_sleep)
before checking for vidout lock

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-09-15 18:47:40 +05:30
..
data vprocss: Align with SSW coding guidelines and few bug fixes 2015-08-24 23:09:53 +05:30
examples vprocss: Add 2 sec wait to example design source files 2015-09-15 18:47:40 +05:30
src vprocss: Add dynamic scaler filter coefficient selection logic 2015-08-30 22:01:58 +05:30