Andrew Zonenberg
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ada98844b9
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greenpak4: Added INT pin to GP_SPI
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2016-12-21 11:35:29 +08:00 |
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Andrew Zonenberg
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6b526e9382
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greenpak4: removed unused MISO pin from GP_SPI
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2016-12-21 11:33:32 +08:00 |
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Andrew Zonenberg
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638f3e3b12
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greenpak4: Removed SPI_BUFFER parameter
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2016-12-20 13:07:49 +08:00 |
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Andrew Zonenberg
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073e8df9f1
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greenpak4: replaced MOSI/MISO with single one-way SDAT pin
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2016-12-20 12:34:56 +08:00 |
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Andrew Zonenberg
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d4a05b499e
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greenpak4: Changed port names on GP_SPI for clarity
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2016-12-20 10:30:38 +08:00 |
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Andrew Zonenberg
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eb80ec84aa
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greenpak4: Initial implementation of GP_SPI cell
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2016-12-20 09:58:02 +08:00 |
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Andrew Zonenberg
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de1d81511a
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greenpak4: Updated GP_DCMP cell model
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2016-12-17 12:01:22 +08:00 |
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Andrew Zonenberg
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7cdba8432c
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greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
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2016-12-16 15:14:20 +08:00 |
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Andrew Zonenberg
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bea6e2f11f
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greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed interface to GP_DCMPMUX
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2016-12-15 15:19:35 +08:00 |
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Andrew Zonenberg
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3690aa556c
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greenpak4: More fixups of GP_DCMPx cells
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2016-12-15 07:19:08 +08:00 |
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Andrew Zonenberg
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3491d33863
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greenpak4: And another typo :(
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2016-12-15 07:17:07 +08:00 |
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Andrew Zonenberg
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ea787e6be3
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greenpak4: Fixed another typo
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2016-12-15 07:16:26 +08:00 |
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Andrew Zonenberg
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58da621ac3
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greenpak4: Fixed typo
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2016-12-15 07:15:38 +08:00 |
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Andrew Zonenberg
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262f8f913c
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greenpak4: Cleaned up trailing spaces in cells_sim
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2016-12-14 14:14:45 +08:00 |
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Andrew Zonenberg
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c77e6e6114
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greenpak4: Added GP_DCMPREF / GP_DCMPMUX
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2016-12-14 14:14:26 +08:00 |
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Andrew Zonenberg
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c3c2983d12
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Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
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2016-12-11 10:04:00 +08:00 |
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Andrew Zonenberg
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8f3d1f8fcf
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greenpak4: Added support for inferred input/output inverters on latches
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2016-12-10 19:58:32 +08:00 |
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Andrew Zonenberg
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c53a33143e
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greenpak4: Can now techmap inferred D latches (without set/reset or output inverter)
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2016-12-10 18:46:36 +08:00 |
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Andrew Zonenberg
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797c03997e
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greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency
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2016-12-10 13:57:37 +08:00 |
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Andrew Zonenberg
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8767cdcac9
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Added GP_DLATCH and GP_DLATCHI
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2016-12-05 23:49:06 -08:00 |
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Andrew Zonenberg
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981f014301
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Initial implementation of techlib support for GreenPAK latches. Instantiation only, no behavioral inference yet.
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2016-12-05 21:22:41 -08:00 |
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Andrew Zonenberg
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e6ab00d419
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Updated help text for synth_greenpak4
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2016-12-05 20:11:37 -08:00 |
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Clifford Wolf
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e9d73d2ee0
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Indenting fixes in gowin sim cell lib
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2016-11-08 18:54:00 +01:00 |
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Clifford Wolf
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3db2ac4e00
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Added hex constant support to write_verilog
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2016-11-03 12:13:23 +01:00 |
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Clifford Wolf
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81bdf0ad0f
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iCE40 flow is not experimental anymore
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2016-11-01 11:32:02 +01:00 |
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Clifford Wolf
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cae5131bac
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Added initial version of "synth_gowin"
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2016-11-01 11:31:13 +01:00 |
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Andrew Zonenberg
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1cca1563c6
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Fixed typo in last commit
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2016-10-18 20:46:49 -07:00 |
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Andrew Zonenberg
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e78fa157a3
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greenpak4: Added GP_PGEN cell definition
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2016-10-18 20:42:44 -07:00 |
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Andrew Zonenberg
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091d32b563
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Added GLITCH_FILTER parameter to GP_DELAY
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2016-10-18 19:53:19 -07:00 |
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Andrew Zonenberg
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a818472f0c
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greenpak4: added model for GP_EDGEDET block
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2016-10-18 19:33:26 -07:00 |
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Andrew Zonenberg
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d6feb4b43e
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greenpak4: Changed parameters for GP_SYSRESET
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2016-10-16 22:53:43 -07:00 |
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Clifford Wolf
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bdc316db50
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Added $anyseq cell type
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2016-10-14 15:24:03 +02:00 |
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Clifford Wolf
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53655d173b
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Added $global_clock verilog syntax support for creating $ff cells
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2016-10-14 12:33:56 +02:00 |
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Clifford Wolf
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8ebba8a35f
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Added $ff and $_FF_ cell types
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2016-10-12 01:18:39 +02:00 |
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Clifford Wolf
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76352c99c9
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Added "prep -nokeepdc"
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2016-09-30 17:02:52 +02:00 |
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Clifford Wolf
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2ee9bf10d0
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Added "prep -nomem"
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2016-08-30 23:57:24 +02:00 |
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Clifford Wolf
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6f41e5277d
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Removed $aconst cell type
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2016-08-30 19:09:56 +02:00 |
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Clifford Wolf
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eae390ae17
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Removed $predict again
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2016-08-28 21:35:33 +02:00 |
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Clifford Wolf
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d77a914683
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Added "wreduce -memx"
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2016-08-20 12:52:50 +02:00 |
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Clifford Wolf
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15ef608453
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Added memory_memx pass, "memory -memx", and "prep -memx"
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2016-08-19 19:48:26 +02:00 |
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Clifford Wolf
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5d90a5b905
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Added greenpak4_dffinv
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2016-08-15 09:33:06 +02:00 |
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Andrew Zonenberg
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0b0ba96488
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greenpak4: Changed name of inverted output ports for consistency
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2016-08-14 00:30:45 -07:00 |
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Andrew Zonenberg
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3b9756c6a3
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greenpak4: Added GP_DFFxI cells
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2016-08-14 00:11:44 -07:00 |
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Andrew Zonenberg
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2b062c48cb
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greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)
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2016-08-13 22:27:58 -07:00 |
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whitequark
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0515809448
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synth_greenpak4: use attrmvcp to move LOC from wires to cells.
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2016-08-10 20:09:35 +00:00 |
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Clifford Wolf
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4056312987
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Added $anyconst and $aconst
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2016-07-27 15:41:22 +02:00 |
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Clifford Wolf
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5c166e76e5
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Added $initstate cell type and vlog function
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2016-07-21 14:23:22 +02:00 |
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Clifford Wolf
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d7763634b6
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After reading the SV spec, using non-standard predict() instead of expect()
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2016-07-21 13:34:33 +02:00 |
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Clifford Wolf
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721f1f5ecf
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Added basic support for $expect cells
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2016-07-13 16:56:17 +02:00 |
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Andrew Zonenberg
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52a738a544
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Added GP_DAC cell
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2016-07-11 22:45:55 -07:00 |
|