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  • ccf7b2e342 Added mxe-based cross build for win32 Clifford Wolf 2014-10-09 10:50:44 +02:00
  • 696d7ed40e Fixes in "hilomap" help message Clifford Wolf 2014-10-08 21:38:37 +02:00
  • 9dea161321 sort cell types in "stat" output by name Clifford Wolf 2014-10-03 19:21:04 +02:00
  • c5c7066ea6 sat encoding for exclusive $pmux ctrl inputs in "share" pass Clifford Wolf 2014-10-03 19:01:24 +02:00
  • 56c1d43408 satgen import sigbit api Clifford Wolf 2014-10-03 18:51:50 +02:00
  • 3e4b0cac8d added resource sharing of $macc cells Clifford Wolf 2014-10-03 12:58:40 +02:00
  • c3e779a65f Added $_BUF_ cell type Clifford Wolf 2014-10-03 10:12:28 +02:00
  • 600c6cb013 remove buffers in opt_clean Clifford Wolf 2014-10-03 10:04:15 +02:00
  • 7019bc00e4 resource sharing of $alu cells Clifford Wolf 2014-10-03 09:55:50 +02:00
  • 2ee03f5da4 set "keep" on modules with $assert cells in "hierarchy" Clifford Wolf 2014-09-30 19:16:40 +02:00
  • 0b8cfbc6fd Added support for "keep" on modules Clifford Wolf 2014-09-29 12:51:54 +02:00
  • f9a307a50b namespace Yosys Clifford Wolf 2014-09-27 16:17:53 +02:00
  • bcd2625a82 Merge pull request #39 from ahmedirfan1983/master Clifford Wolf 2014-09-22 12:37:43 +02:00
  • d3c67ad9b6 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Ahmed Irfan 2014-09-22 11:35:04 +02:00
  • 13117bb346 Re-enabled assert for new logic loops in "share" pass Clifford Wolf 2014-09-21 19:44:08 +02:00
  • 96e821dc6c Various improvements regarding logic loops in "share" results Clifford Wolf 2014-09-21 19:36:56 +02:00
  • d6e2ace95b Logic loop bugfix for "share" pass Clifford Wolf 2014-09-21 15:13:44 +02:00
  • b28be0759f Added "share -limit" Clifford Wolf 2014-09-21 15:13:06 +02:00
  • a6c08b40fe Still loop bug in "share": changed assert to warning Clifford Wolf 2014-09-21 14:51:07 +02:00
  • 8d60754aef Do not introduce new logic loops in "share" Clifford Wolf 2014-09-21 13:52:39 +02:00
  • edf11c635a Assert on new logic loops in "share" pass Clifford Wolf 2014-09-21 12:57:33 +02:00
  • a7758ef953 Added "test_abcloop" command Clifford Wolf 2014-09-19 15:51:34 +02:00
  • 00964f2f61 Initialize RTLIL::Const from std::vector<bool> Clifford Wolf 2014-09-19 15:50:55 +02:00
  • 309623ff17 Sorting of object names in ilang backend Clifford Wolf 2014-09-19 15:50:34 +02:00
  • 5827826098 Small improvements in "abc" command handle_loops() function Clifford Wolf 2014-09-19 14:05:41 +02:00
  • 3aa003c8e9 Using "NOT" instead of "INV" as cell name in default abc genlib file Clifford Wolf 2014-09-19 13:15:31 +02:00
  • f7bb8f244b Alphabetically sort port names in "show" output Clifford Wolf 2014-09-19 11:13:10 +02:00
  • f56b92818b Do not run "scorr" in "abc -fast" Clifford Wolf 2014-09-18 19:00:21 +02:00
  • 4888d61c65 Improvements in "synth" script Clifford Wolf 2014-09-18 12:57:55 +02:00
  • 815fab9d71 Added "abc -fast" Clifford Wolf 2014-09-18 12:57:37 +02:00
  • b783dbe148 fixed memory next issue, when same memory is written in different case statement fixed reduce_xnor, logic_not bug translation bug ahmedirfan1983 2014-09-18 11:15:46 +02:00
  • ba61925071 Added commit count to devel version number Clifford Wolf 2014-09-17 07:19:34 +02:00
  • 9ae559b990 Fixed $_NOR vs. $_NOR_ typo in abc.cc Clifford Wolf 2014-09-16 12:45:05 +02:00
  • ae02d9cb9a Fixed $memwr/$memrd order in memory_dff Clifford Wolf 2014-09-16 12:40:58 +02:00
  • fa96cf4a16 Added new CodingReadme file (replaces CodingStyle and CHECKLISTS) Clifford Wolf 2014-09-16 11:26:44 +02:00
  • 6644e27cd4 Fixed $macc simlib model for zero-config Clifford Wolf 2014-09-16 08:19:35 +02:00
  • b86410b2ab More aggressive $macc merging in alumacc Clifford Wolf 2014-09-15 12:42:11 +02:00
  • b470c480e9 Added the obvious optimizations to alumacc $macc generator Clifford Wolf 2014-09-15 12:22:03 +02:00
  • fcbda07411 Improved maccmap tree bit packing Clifford Wolf 2014-09-15 12:00:19 +02:00
  • 2cbdbaad1f Fixed wreduce $shiftx handling Clifford Wolf 2014-09-15 11:29:09 +02:00
  • 2442eb3832 Fixed monitor notifications for removed cell Clifford Wolf 2014-09-14 17:04:39 +02:00
  • 7815f81c32 Added "synth" command Clifford Wolf 2014-09-14 16:09:06 +02:00
  • 7e156a5419 Fixed techmap_wrap for techmap_celltype Clifford Wolf 2014-09-14 15:34:36 +02:00
  • 923bbbeaf0 Using alumacc in techmap.v Clifford Wolf 2014-09-14 14:50:15 +02:00
  • 014bb34e0e Various fixes/cleanups in alumacc and maccmap Clifford Wolf 2014-09-14 14:49:53 +02:00
  • 124e759280 Added techmap_wrap attribute Clifford Wolf 2014-09-14 14:49:26 +02:00
  • b34ca15185 alumacc fix for $pos cells Clifford Wolf 2014-09-14 14:00:14 +02:00
  • 0df1d9ad72 Extract $alu cells in alumacc Clifford Wolf 2014-09-14 13:23:44 +02:00
  • 7b16c63101 Merge $macc cells in alumacc pass Clifford Wolf 2014-09-14 11:21:37 +02:00
  • 0b72f0acb1 Basic $macc extract in alumacc Clifford Wolf 2014-09-14 10:45:28 +02:00
  • ff157fb74f alumacc skeleton Clifford Wolf 2014-09-14 10:02:00 +02:00
  • aab0e3bf70 Cleanup in wreduce Clifford Wolf 2014-09-14 10:01:30 +02:00
  • 3ae96f85a5 Using pkg-config to find libffi Clifford Wolf 2014-09-13 17:28:15 +02:00
  • 44b5bd4b63 Fixed simlib $macc model for xilinx xsim Clifford Wolf 2014-09-08 17:09:39 +02:00
  • fcb46138ce Simplified $fa undef model Clifford Wolf 2014-09-08 16:59:39 +02:00
  • 6dc07eb1f2 Fixes and cleanups for blackbox.v Clifford Wolf 2014-09-08 13:29:13 +02:00
  • af0c8873bb Added $lcu cell type Clifford Wolf 2014-09-08 13:28:23 +02:00
  • 48b00dccea Another $clog2 bugfix Clifford Wolf 2014-09-08 12:25:23 +02:00
  • d46bac3305 Added "$fa" cell type Clifford Wolf 2014-09-08 12:15:39 +02:00
  • 1a88e47396 Trim msb/lsb zero bits from full adder in maccmap Clifford Wolf 2014-09-08 11:21:58 +02:00
  • 6747a7047e Added "test_cell -const" Clifford Wolf 2014-09-08 11:12:39 +02:00
  • dd887cc025 Using maccmap for $macc and $mul techmap Clifford Wolf 2014-09-07 18:24:08 +02:00
  • c50b841b29 Added 'techmap_maccmap' techmap attribute Clifford Wolf 2014-09-07 18:23:37 +02:00
  • 015dcdc84c Added "maccmap" command Clifford Wolf 2014-09-07 18:23:04 +02:00
  • 15b3c54fea Added "test_cell -nosat" Clifford Wolf 2014-09-07 17:05:41 +02:00
  • 9329a76818 Various bug fixes (related to $macc model testing) Clifford Wolf 2014-09-06 20:30:46 +02:00
  • 98e6463ca7 Added $macc eval model Clifford Wolf 2014-09-06 19:44:28 +02:00
  • fa64942018 Added $macc SAT model Clifford Wolf 2014-09-06 19:44:11 +02:00
  • 680eaaac41 Fixed $clog2 (off by one error) Clifford Wolf 2014-09-06 19:31:04 +02:00
  • bff4706b62 Added $macc simlib model (also use as techmap rule for now) Clifford Wolf 2014-09-06 17:59:12 +02:00
  • deff416ea7 Fixed assignment of out-of bounds array element Clifford Wolf 2014-09-06 17:58:27 +02:00
  • b847ec8a0b Added $macc cell type Clifford Wolf 2014-09-06 15:47:46 +02:00
  • 76f8128123 Fixed autotest for non-basename arguments Clifford Wolf 2014-09-06 12:10:57 +02:00
  • 34af6a1303 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-09-06 11:46:44 +02:00
  • e1743b3bac Added "test_cell -script" Clifford Wolf 2014-09-06 11:46:07 +02:00
  • 652345c9cd Merge pull request #38 from rubund/master Clifford Wolf 2014-09-06 10:15:47 +02:00
  • 79cbf9067c Corrected spelling mistakes found by lintian Ruben Undheim 2014-09-06 08:47:06 +02:00
  • 01ef34c147 Added tests/various/constmsk_test.ys Clifford Wolf 2014-09-04 15:07:30 +02:00
  • f5a40e7043 Fixed "opt_const -fine" for $pos cells Clifford Wolf 2014-09-04 08:55:58 +02:00
  • 8927aa6148 Removed $bu0 cell type Clifford Wolf 2014-09-04 02:07:52 +02:00
  • b9cb483f3e Using $pos models for $bu0 Clifford Wolf 2014-09-03 21:20:59 +02:00
  • 5733f4a39d Fixed "test_cells -vlog" Clifford Wolf 2014-09-03 13:43:37 +02:00
  • 50ac284823 Fixes in $alu SAT- and eval-models Clifford Wolf 2014-09-03 13:39:46 +02:00
  • 635b922afe Undef-related fixes in simlib $alu model Clifford Wolf 2014-09-02 23:21:59 +02:00
  • f1869667ca Improvements in "test_cell -vlog" Clifford Wolf 2014-09-02 23:21:15 +02:00
  • 66bf2bb92e Added test_cell -vlog Clifford Wolf 2014-09-02 22:49:43 +02:00
  • da360771a1 Create a default selection stack in RTLIL::Design::Design() Clifford Wolf 2014-09-02 22:49:24 +02:00
  • c38283dbd0 Small bug fixes in $not, $neg, and $shiftx models Clifford Wolf 2014-09-02 17:48:41 +02:00
  • acd7a99aef Added SAT testing to test_cell eval stage Clifford Wolf 2014-09-02 17:28:13 +02:00
  • 2446b6fbef added $pmux cell translation Ahmed Irfan 2014-09-02 14:47:51 +02:00
  • 37fe7c7bdf Removed references to yosys-svgviewer from docs Clifford Wolf 2014-09-02 04:03:06 +02:00
  • ee29ae2206 Removed yosys-svgviewer Clifford Wolf 2014-09-02 03:52:46 +02:00
  • 9f00a0cd2d Using "xdot" instead of "yosys-svgviewer" in show command Clifford Wolf 2014-09-02 03:28:46 +02:00
  • 630befdf6d Added $alu support to test_cell Clifford Wolf 2014-09-01 16:36:04 +02:00
  • 2fcf66b91d Added ConstEval model for $alu cells Clifford Wolf 2014-09-01 16:35:46 +02:00
  • bae09dca2b Added SAT model for $alu cells Clifford Wolf 2014-09-01 16:35:25 +02:00
  • 9923762461 Fixed "test_cell -simlib all" Clifford Wolf 2014-09-01 15:37:56 +02:00
  • c7f81e4e49 Added "test_cell -simlib -v" Clifford Wolf 2014-09-01 15:37:21 +02:00
  • 826fdb34d8 Added "techmap -autoproc" Clifford Wolf 2014-09-01 15:36:29 +02:00
  • 27a1bfbec6 Fixes in old SAT example.ys Clifford Wolf 2014-09-01 11:45:47 +02:00