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  • 0515809448 synth_greenpak4: use attrmvcp to move LOC from wires to cells. whitequark 2016-08-10 20:09:35 +00:00
  • e9fe57c75e Only allow posedge/negedge with 1 bit wide signals Clifford Wolf 2016-08-10 19:32:11 +02:00
  • 73b7232ec8 Fixed some compiler warnings in attrmap command Clifford Wolf 2016-08-10 13:44:08 +02:00
  • b0aab4e304 Added "attrmap" command Clifford Wolf 2016-08-09 19:56:55 +02:00
  • 39da8eddae Added log_const() API Clifford Wolf 2016-08-09 19:56:10 +02:00
  • 3c6d31fd06 Added "attrmvcp" pass Clifford Wolf 2016-08-09 11:18:48 +02:00
  • f7730d43bb Use /proc/self/exe on Cygwin as well. Yury Gribov 2016-08-07 21:34:33 +01:00
  • 9d15529214 Undo "preserve wire attributes in iopadmap" change (it was OK before) Clifford Wolf 2016-08-08 11:47:35 +02:00
  • 88a67afa7d Added "test_autotb -seed" (and "autotest.sh -S") Clifford Wolf 2016-08-06 13:32:29 +02:00
  • 90c17aad56 preserve wire attributes in iopadmap Clifford Wolf 2016-08-06 13:24:59 +02:00
  • 7f755dec75 Fixed bug in parsing real constants Clifford Wolf 2016-08-06 13:16:23 +02:00
  • 5d6765a9d2 Added "insbuf" command Clifford Wolf 2016-08-02 10:37:19 +02:00
  • 21e1bac084 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2016-07-30 12:50:39 +02:00
  • 5fe13a16ea Added "write_verilog -defparam" Clifford Wolf 2016-07-30 12:46:06 +02:00
  • 7fa61cba1b Added "write_verilog -nodec -nostr" Clifford Wolf 2016-07-30 12:38:40 +02:00
  • da56a5bbc6 Added $initstate support to smtbmc flow Clifford Wolf 2016-07-27 16:11:37 +02:00
  • 8d88fcb270 Added SatGen support for $anyconst Clifford Wolf 2016-07-27 15:52:20 +02:00
  • 9540be1d45 Removed $predict support from SatGen Clifford Wolf 2016-07-27 15:44:11 +02:00
  • 4056312987 Added $anyconst and $aconst Clifford Wolf 2016-07-27 15:41:22 +02:00
  • a7b0769623 Added "read_verilog -dump_rtlil" Clifford Wolf 2016-07-27 15:40:17 +02:00
  • 8537c4d206 Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() Clifford Wolf 2016-07-25 16:39:25 +02:00
  • 5b944ef11b Fixed a verilog parser memory leak Clifford Wolf 2016-07-25 16:37:58 +02:00
  • 7a67add95d Fixed parsing of empty positional cell ports Clifford Wolf 2016-07-25 12:48:03 +02:00
  • b1c432af56 Improvements in CellEdgesDatabase Clifford Wolf 2016-07-24 17:21:53 +02:00
  • f162b858f2 Added CellEdgesDatabase API Clifford Wolf 2016-07-24 13:59:57 +02:00
  • 54966679df Moved SatHelper::setup_init() code to SatHelper::setup() Clifford Wolf 2016-07-24 12:18:39 +02:00
  • 34e833103b Added $initstate support to "sat" command Clifford Wolf 2016-07-23 17:01:03 +02:00
  • 9aae1d1e8f No tristate warning message for "read_verilog -lib" Clifford Wolf 2016-07-23 11:56:53 +02:00
  • 89deb412c6 Added satgen initstate support Clifford Wolf 2016-07-22 10:28:45 +02:00
  • 7fef5ff104 Using $initstate in "initial assume" and "initial assert" Clifford Wolf 2016-07-21 14:37:28 +02:00
  • 5c166e76e5 Added $initstate cell type and vlog function Clifford Wolf 2016-07-21 14:23:22 +02:00
  • d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() Clifford Wolf 2016-07-21 13:34:33 +02:00
  • 721f1f5ecf Added basic support for $expect cells Clifford Wolf 2016-07-13 16:56:17 +02:00
  • b3155af5f6 Added examples/smtbmc Clifford Wolf 2016-07-13 09:49:05 +02:00
  • 2afc72cae3 Merge pull request #191 from whitequark/json-module-attributes Clifford Wolf 2016-07-13 09:39:27 +02:00
  • 9e5c9471e3 Merge pull request #193 from azonenberg/master Clifford Wolf 2016-07-13 09:24:31 +02:00
  • 32bea97b75 Merge https://github.com/cliffordwolf/yosys Andrew Zonenberg 2016-07-12 16:12:37 -07:00
  • e92998a79c Minor bugfix in FSM reset state detection Clifford Wolf 2016-07-12 09:46:15 +02:00
  • 546233f0e1 write_json: also write module attributes. whitequark 2016-07-12 06:32:04 +00:00
  • 52a738a544 Added GP_DAC cell Andrew Zonenberg 2016-07-11 22:45:55 -07:00
  • baae472b83 Removed VOUT port of GP_BANDGAP Andrew Zonenberg 2016-07-11 22:45:42 -07:00
  • 8619d33114 Removed splitnets in prep for new gp4par parser Andrew Zonenberg 2016-07-11 22:42:25 -07:00
  • c71785d65e Yosys-smtbmc: Support for hierarchical VCD dumping Clifford Wolf 2016-07-11 12:49:33 +02:00
  • 0153ad85d9 Moved smt2 yosys info parsing from smtbmc.py to smtio.py Clifford Wolf 2016-07-11 11:49:05 +02:00
  • cdb58f68ab Added "prep -auto-top" and "synth -auto-top" Clifford Wolf 2016-07-11 11:40:55 +02:00
  • a72fb85dc2 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2016-07-10 18:17:09 +02:00
  • 307e31a95e Merge pull request #189 from whitequark/master Clifford Wolf 2016-07-10 18:12:00 +02:00
  • 771c5fe000 Support for hierarchical designs in smt2 back-end Clifford Wolf 2016-07-10 18:11:25 +02:00
  • c0645839fe greenpak4: add GP_COUNT{8,14}_ADV cells. whitequark 2016-07-10 14:41:34 +00:00
  • b5a9fba0db Further improved fsm_detect output, attempt to detect self-resetting circuits Clifford Wolf 2016-07-09 14:02:49 +02:00
  • d63ffabacb Added printing of some warning messages to fsm_detect Clifford Wolf 2016-07-09 13:23:06 +02:00
  • d3f0d72427 Added warning about adding fsm_encoding attributes to wires to manual Clifford Wolf 2016-07-08 18:31:31 +02:00
  • 21659847a7 Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations Clifford Wolf 2016-07-08 14:41:36 +02:00
  • 9a101dc1f7 Fixed mem assignment in left-hand-side concatenation Clifford Wolf 2016-07-08 14:31:06 +02:00
  • b782076698 Merge branch 'eddiehung-vtr' Clifford Wolf 2016-07-08 11:56:53 +02:00
  • 27b5347a87 Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior Clifford Wolf 2016-07-08 11:49:55 +02:00
  • 72149aba2e In BLIF, a .names without entries already always outputs 0 Clifford Wolf 2016-07-08 11:41:26 +02:00
  • 6bda612925 Undo eddiehung-vtr Makefile changes Clifford Wolf 2016-07-08 11:35:15 +02:00
  • f6b7cf23d6 Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddiehung-vtr Clifford Wolf 2016-07-08 11:32:36 +02:00
  • e420412043 Fixed autotest.sh handling of `timescale Clifford Wolf 2016-07-02 13:32:20 +02:00
  • 080f95f933 Merge branch 'assert-limit' Clifford Wolf 2016-07-01 12:24:31 +02:00
  • 6ed6b3cb6d Replaced "select -assert-limit" with -assert-max and -assert-min Clifford Wolf 2016-07-01 12:24:13 +02:00
  • 9a742f4069 Added 'assert-limit' option for 'select' command eshellko 2016-07-01 10:24:22 +04:00
  • df5ebfa0a0 Improved ice40_ffinit error reporting Clifford Wolf 2016-06-30 09:58:13 +02:00
  • 7cddab0788 Merge pull request #181 from rubund/input_logic_allowed Clifford Wolf 2016-06-21 08:44:20 +02:00
  • 545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog Ruben Undheim 2016-06-20 20:16:37 +02:00
  • 541083cf32 Bugfix in "abc -script" handling Clifford Wolf 2016-06-19 22:19:19 +02:00
  • 9bca8ccd40 Merge branch 'sv_packages' of https://github.com/rubund/yosys Clifford Wolf 2016-06-19 15:48:40 +02:00
  • ca91bccb6b Added "deminout" Clifford Wolf 2016-06-19 13:08:16 +02:00
  • a8200a773f A few modifications after pull request comments Ruben Undheim 2016-06-18 14:13:36 +02:00
  • 9e28290b0f Added "read_blif -sop" Clifford Wolf 2016-06-18 12:33:13 +02:00
  • 5ffad4e073 Added $sop support to BLIF back-end Clifford Wolf 2016-06-18 12:28:49 +02:00
  • 178ff3e7f6 Added support for SystemVerilog packages with localparam definitions Ruben Undheim 2016-06-18 10:24:21 +02:00
  • 3380281e15 Added "dc2" to default ABC scripts Clifford Wolf 2016-06-17 20:15:35 +02:00
  • 7a4ee5da74 Fixed init issue in mem2reg_test2 test case Clifford Wolf 2016-06-17 20:15:11 +02:00
  • f498204ae4 Added "abc -I <num> -P <num>" Clifford Wolf 2016-06-17 19:39:35 +02:00
  • ebece2b8d5 Added $sop SAT model Clifford Wolf 2016-06-17 17:47:30 +02:00
  • 95757efb25 Improved support for $sop cells Clifford Wolf 2016-06-17 16:31:16 +02:00
  • 52bb1b968d Added $sop cell type and "abc -sop" Clifford Wolf 2016-06-17 13:46:01 +02:00
  • c3365034e9 Updated ABC to hg rev b5df6e2b76f0 Clifford Wolf 2016-06-17 11:16:31 +02:00
  • 99edf24966 Added "nlutmap -assert" Clifford Wolf 2016-06-09 11:47:41 +02:00
  • 52b0b4e31e Do not run "wreduce" in "prep -ifx" Clifford Wolf 2016-06-08 12:14:32 +02:00
  • 2032e6d8e4 Added "proc_mux -ifx" Clifford Wolf 2016-06-06 17:15:50 +02:00
  • dcf576641b Added "setundef -init" Clifford Wolf 2016-06-03 11:38:31 +02:00
  • d2695e2bfa Fix all undef-muxes in dlatch input cone Clifford Wolf 2016-06-02 14:37:07 +02:00
  • adfc80727c Avoid creating undef-muxes when inferring latches in proc_dlatch Clifford Wolf 2016-06-01 13:25:06 +02:00
  • 11f7b8a2a1 Added opt_expr support for div/mod by power-of-two Clifford Wolf 2016-05-29 12:17:36 +02:00
  • 766032c5f8 Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} Clifford Wolf 2016-05-27 17:55:03 +02:00
  • ee071586c5 Fixed access-after-delete bug in mem2reg code Clifford Wolf 2016-05-27 17:25:33 +02:00
  • e9ceec26ff fixed typos in error messages Clifford Wolf 2016-05-27 16:37:36 +02:00
  • 611f121cb9 Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop Clifford Wolf 2016-05-27 16:33:13 +02:00
  • 33742f4e8f Merge pull request #172 from zeldin/deterministic_hierarchy Clifford Wolf 2016-05-22 18:15:08 +02:00
  • e22e4d59b8 Made the expansion order of hierarchy deterministic Marcus Comstedt 2016-05-22 16:37:47 +02:00
  • 8e9e793126 Some fixes in tests/asicworld/*_tb.v Clifford Wolf 2016-05-20 17:13:11 +02:00
  • 1e227caf72 Improvements and fixes in autotest.sh script and test_autotb Clifford Wolf 2016-05-20 16:58:02 +02:00
  • 884ec96787 Merge branch 'master' of https://github.com/Kmanfi/yosys Clifford Wolf 2016-05-20 16:48:50 +02:00
  • f3983a0940 Also escape "=" in spice output Clifford Wolf 2016-05-20 16:43:13 +02:00
  • 060bf4819a Small improvements in Verilog front-end docs Clifford Wolf 2016-05-20 16:21:35 +02:00
  • 8c3bc2ac0d Close opened dump file. Kaj Tuomi 2016-05-19 11:53:29 +03:00
  • f6221ade95 Fix for Modelsim transcript line warp issue #164 Kaj Tuomi 2016-05-19 11:34:38 +03:00