Mirrors/VILLASnode
1
0
Fork 0
mirror of https://git.rwth-aachen.de/acs/public/villas/node/ synced 2025-03-09 00:00:00 +01:00
Code Issues Releases Wiki Activity
6319 commits 171 branches 31 tags 76 MiB
Commit graph

24 commits

Author SHA1 Message Date
Niklas Eiling
5dd12eafc4 fpga: Apply suggestions from code review 
Co-authored-by: Steffen Vogel <steffen.vogel@opal-rt.com>
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
e9b1a4a528 fpga: improve comments 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
ce0959d4ba fpga: Clean up dino.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
bf2b18bf47 fpga: Add new Dino configuration register that allows triggering the DAC before the time step to dino.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2025-01-24 10:32:57 +01:00
Niklas Eiling
eeeb9b1d7b dino: fix wrong copyright notice in dino.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-26 10:09:01 +02:00
Niklas Eiling
f25e1dd689 log: fix undefined intitialization order of static objects. fixes #799. 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-05 14:57:13 +02:00
Niklas Eiling
5f44e16ced fpga: remove dead code and improve comments in Dino IP 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
136d033cd3 fpga: fix dino setting wrong offset value to float converter 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
7991d31393 fpga/dino: add and set new registers 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
973834b3aa fpga: use constants to access registers 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
0c3a9f4729 fpga: convert SignalType to string before printing 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
12af65b2b4 fpga: move register config for dino to DinoAdc 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
d588f5f2a2 dino: use enum instead of literal for GAIN 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 11:50:44 +01:00
Niklas Eiling
8b95182b08 automatically configure and test Dino based on hwdef json 
this currently requires manually adding the mapping of Dinos to i2c
buses in the fpga json.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d4a868ae7c Dino: add debug output for direction registers of io extender 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
db062f08bd Dino: overload operator>> for IoextPorts 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
60c65c2880 verify more assumptions in i2c 
add selftest to I2c and readback Dino configuration to verify it was
actually set

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
335dd2c0ce fix bug where Dino IP always read 0 from i2c. Add hardware mutex to I2c 
and to I2c::Switch

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
acaa4dd9de improve i2c IP 
more code reuse, add function for reading from a register i.e. combined
write and read

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
dbe4e4e472 add i2c configuration logic to dino IP 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Steffen Vogel
157d5b21d7 Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82) 
This edits the headers in every file so the copyright notice mentions RWTH Aachen University. We also update some copyright years and fix various comments so the header is the same across all of VILLASframework.

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

---------

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-09-08 11:35:18 +02:00
Steffen Vogel
9b27c31b9c fixup copyright texts 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:32:48 +01:00
Steffen Vogel
f776cba693 relicense project to Apache 2.0 
The project is now also REUSE compliant: https://reuse.software/
Previous copyright holders have provided their
acknowledgement to transition to the new license in the
following GitHub PR: https://github.com/VILLASframework/fpga/pull/66

Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-07 17:20:15 +01:00
Steffen Vogel
53ddbe4e10 refactor registration of IP core drivers to be aligned with registration of VILLASnode formats and node-types 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-05 14:21:20 +01:00