Niklas Eiling
bb820d8909
fpga: add --timestep option to villas-fpga-ctrl
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-11-13 10:25:06 +01:00
e5ab276566
fix: Formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-11-04 10:30:14 +01:00
Pascal Bauer
d521b5567f
feat: add json parsing of iplist
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-10-31 15:21:30 +01:00
Pascal Bauer
c577e8a2a1
review: remove comment, change loglevel
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-10-31 15:21:30 +01:00
Pascal Bauer
5e23100df9
feat: add parsing for ip-ignorelist
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-10-31 15:21:30 +01:00
Pascal Bauer
ee83bb197b
feat: ips can be ignored to be initialized in corefactory
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-10-31 15:21:30 +01:00
Steffen Vogel
1520743f73
fix: Formatting with clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-10-31 12:18:20 +01:00
Steffen Vogel
28d354cb84
Fix formatting with clang-format
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-10-15 19:31:49 +02:00
Pascal Bauer
83e95f88a5
Refactor: change namespace pci to devices
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-08-30 12:23:02 +02:00
Pascal Bauer
c41f91f1ca
refactor: rename DeviceList to PciDeviceList
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-08-30 12:23:02 +02:00
Pascal Bauer
975c02dc7d
Refactor: rename pci class to pci_device
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-08-30 12:23:02 +02:00
Pascal Bauer
91b541943e
Refactor: Move pci to devices/pci_device
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-08-30 12:23:02 +02:00
Niklas Eiling
97fccd604d
PCIeCard: load correct kernel module
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
Niklas Eiling
eeeb9b1d7b
dino: fix wrong copyright notice in dino.cpp
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-26 10:09:01 +02:00
IgnoreWarnings
2bc2eaed28
ensure loading of vfio modules
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Signed-off-by: IgnoreWarnings <pascal.bauer@rwth-aachen.de>
2024-08-09 09:14:47 +02:00
Niklas Eiling
f25e1dd689
log: fix undefined intitialization order of static objects. fixes #799 .
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-05 14:57:13 +02:00
Pascal Bauer
74155d9685
add optional indicator
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-31 11:54:16 +02:00
Pascal Bauer
9e89ba32c2
make baseaddress optional, remove debug output
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-31 11:54:16 +02:00
Niklas Eiling
5f44e16ced
fpga: remove dead code and improve comments in Dino IP
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
7128da24c3
fpga: make dma able to handle sequence numbers generated in the FPGA
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
136d033cd3
fpga: fix dino setting wrong offset value to float converter
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
7991d31393
fpga/dino: add and set new registers
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Pascal Bauer
f364db1748
add parsing for baseaddress
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-29 11:29:03 +02:00
Pascal Bauer
81f8981783
add member and getter for baseaddress
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-29 11:29:03 +02:00
Pascal Bauer
54796d11b2
removed void indicator
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
80fa0429dd
change name of "parseVLNV" to "parseIpIdentifier"
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
ba92d5447f
add linebrakes
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
f79f7f4ca7
refactor make
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
7d37c56947
move ip initialization into function
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
05f7a03909
move configure ips into function
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
cb53713953
move reordering of ips into function
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
823ba3281e
move VLNV parsing to function
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Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Niklas Eiling
aeda901e47
fpga: use separate locks for write and read to allow them to be used concurrently
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-05 12:30:24 +02:00
Niklas Eiling
973834b3aa
fpga: use constants to access registers
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
0c3a9f4729
fpga: convert SignalType to string before printing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
34bca6826b
fpga: make dino sampling rate configurable at top level and via json
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
12af65b2b4
fpga: move register config for dino to DinoAdc
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
4911c96d8d
fpga: update libxil subreport so we support 64-bit addressing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
21221eb698
fpga: fix empty search path being an error
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
a366b80109
Fix formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
Niklas Eiling
ed05671a51
fpga: improve comments in register.cpp
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
c151be5cca
fpga: fix includes and various comments
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
f1776f8be4
fpga: improve comments for fastRead and fastWrite
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
2cc8cad115
fpga: expose methods for finer control over DMA data path
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d
fpga: improve dma latency
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
483293aec8
fpga: turn off all interrupts when using polling
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this improves the latency by at least 4 us in my setup.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
57d7396c09
fpga: optimize sg descriptor rings
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we are now using only one memory block for both sg rings. This is
required so that the SG interface can benefit from a read cache
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
a2d55a9b6e
Harmonize descriptions of plugins
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:06:15 +02:00
e032c9857c
thirdparty: Update CLI11
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
936830d484
Remove unused includes and variables
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
