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645 commits

Author SHA1 Message Date
Niklas Eiling
edb996ebfd add fmt::formatter for Dino::IoextPorts 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
645429b9c8 lib/CMakeLists.txt: fix error in syntax 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-12 12:01:51 +01:00
Niklas Eiling
b2fcfeaa67 move more of the switch configuration boilerplate into ConnectString 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-12 11:46:59 +01:00
Niklas Eiling
147725daef libvillas-fpga.so: only link with stdc++fs for gcc8 and earlier 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-12 11:46:59 +01:00
Niklas Eiling
ca6c70e09b ConnectString: Make channel data type more generic 
we can not only connect Aurora channels to the switch so use Node
instead as the data type

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-12 11:46:59 +01:00
Niklas Eiling
1c2d8e440b update and reformat villas-fpga-ctrl 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
897d916886 Core/Card: enable IP init requiring other IPs 
add initialized IP to card->ips already during initialization so that
later IPs can use early initiliazed IPs to do their initilization.
E.g. Dino needs I2c for initialization.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
8b95182b08 automatically configure and test Dino based on hwdef json 
this currently requires manually adding the mapping of Dinos to i2c
buses in the fpga json.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
b5682290c2 I2c: use Switch::selfTest to check i2c bus 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d4a868ae7c Dino: add debug output for direction registers of io extender 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
db062f08bd Dino: overload operator>> for IoextPorts 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
60c65c2880 verify more assumptions in i2c 
add selftest to I2c and readback Dino configuration to verify it was
actually set

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
335dd2c0ce fix bug where Dino IP always read 0 from i2c. Add hardware mutex to I2c 
and to I2c::Switch

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
acaa4dd9de improve i2c IP 
more code reuse, add function for reading from a register i.e. combined
write and read

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
08b666a548 make I2c destructor call to I2c::reset explicit 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
dbe4e4e472 add i2c configuration logic to dino IP 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
810b1259f8 fix double start of i2c bus driver and move channel map to header 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
48846ace39 i2c: add handling of BusNotBusy interrupt on reads. add retrying of 
channel reads in case inconsistent state was detected.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
f086c325c2 link with stdc++fs to avoid compiler error on newer gcc versions 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
57177c074e fix several issues with i2c implementation and add support for 
interacting with i2c switches

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
2d51deea0c remove vfio container intitialization from setupFPGACard 
this lead to double creation of the vfio container

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
3e74c0d7a4 remove linking to libjansson from libvillas-fpga because this is already 
included in libvillas-common.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
1578a26915 i2c: fix missing getMemoryBlocks method leading to unmapped memory 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d34ab182e4 fix unmapped ring buffers in dma.cpp leading to segfault 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
e93b8e998d fix IPs without stream port causing an error and fix formatting in 
node.cpp

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
bd1f32da7b fix fomatting in core.cpp 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
64d5a6ba42 fpgas.json: switch to new json per default and fix the same 
use fpga definition that includes dino and i2c controller to use the
latest bitstream (vc707-xbar-pcie-dino).
Fix the json for that bitstream to also include the interrupt
controller.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
3e64e5d238 hwdef-parse.py: add interrupt controller added as module_ref to 
whitelist

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
7e07da6e60 add i2c ip draft 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
0138119bff copy new editorconf from node 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d61337023e add draft for i2c drvier implementation 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:17:26 +01:00
Niklas Eiling
ba71f6384f hwdef-parse.py: add SPDX compliant license info 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:11:26 +01:00
Niklas Eiling
4f4312127d add json for vc707-xbar-pcie-dino 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:11:26 +01:00
Niklas Eiling
ada7cac017 hwdef-parse.py: whitelist iic and DINO IPs 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:11:26 +01:00
Niklas Eiling
e2382c643b add hwdef-parse script from hardware repo 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:11:26 +01:00
Niklas Eiling
2967fb8ac9 fix fpga.cpp unit test failing due to changed DeviceList interface 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Niklas Eiling
654ee84e9e make FPGA device interface agnostic 
remove explicit mentioning of PCIe in the use of Device as a preparation
for integrating platform devices. auto formatted some files.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Niklas Eiling
7ce1ee5a6c make villas-fpga-ctrl accept multiple connect strings 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Niklas Eiling
804f3eea29 update common subrepo 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Philipp Jungkamp
e2c2ec2c8b Fix fmt 10.0.0 related formatting errors. 
Signed-off-by: Philipp Jungkamp <p.jungkamp@gmx.net>
 2023-09-26 17:00:31 +02:00
Steffen Vogel
157d5b21d7 Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82) 
This edits the headers in every file so the copyright notice mentions RWTH Aachen University. We also update some copyright years and fix various comments so the header is the same across all of VILLASframework.

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

---------

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-09-08 11:35:18 +02:00
Niklas Eiling
c2176113d7 update libxil submodule 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-09-08 11:24:43 +02:00
Niklas Eiling
a5991bc794 deactivate stric-aliasing for cast 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-07-25 18:26:19 +02:00
Niklas Eiling
c84df46d9e update libxil submodule, adding correct install path for libxil 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-07-25 17:36:01 +02:00
Niklas Eiling
d9993409e0 fix possible NULL dereferencing in villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 14:56:54 +01:00
Niklas Eiling
1d9ccd6c05 add license note to villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:59:22 +01:00
Niklas Eiling
9d4cd5384d clean up debuggin output and fix scanf usage in villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:52:36 +01:00
Niklas Eiling
d273162f71 fix PCIeCardFactory looking for IP config file at the wrong location 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:29:32 +01:00
Niklas Eiling
d9e60e22b1 make it possible to specify a search path in PcieCard::make so we can use relative paths in config files 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:15:25 +01:00
Niklas Eiling
c05ae4d282 add C bindings for DMA interactions and add a test/example 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 10:47:45 +01:00