Daniel Krebs
10745f00b5
libxil: update submodule
...
Only add temporary files to gitignore
2018-02-13 16:15:28 +01:00
Daniel Krebs
409340433d
enable -Wall, -Wextra and -Werror and fix new errors ( fixes #20 )
2018-02-13 16:04:34 +01:00
Daniel Krebs
6dab50824b
directed-graph: fix bug in loop detection
2018-02-13 09:54:31 +01:00
8206f867a5
logging: use similar log style in all modules
2018-01-31 20:24:11 +01:00
2336acaf98
tests: override some criteriod_log() functions in order to use spdlog style log output
2018-01-31 20:23:48 +01:00
51a3d0b8e9
tests: some cleanups
2018-01-31 20:22:15 +01:00
2a03d19d53
tests: readd missing graph test suite
2018-01-31 15:12:36 +01:00
b0f4577dd3
tests: automatically detect whether or not we can run tests in parallel
2018-01-31 15:12:19 +01:00
0aed1a1b12
tests: moved initialization of FPGA stuff to fpga.cpp
2018-01-31 15:11:13 +01:00
Daniel Krebs
32be16ef98
tests/graph: move criterion setup to from main.cpp to graph.cpp
2018-01-31 11:21:02 +01:00
Daniel Krebs
3de2170ad6
tests: move variables to global state and set criterion jobs to 1
2018-01-31 11:17:21 +01:00
1b6d0d7700
Merge branch 'feature/hw-testing' into feature/cpp ( closes #14 and #15 )
2018-01-30 19:38:49 +01:00
3c7f6e968b
do parallel build
2018-01-30 19:36:39 +01:00
e25a3e24bc
cleanup build dir before building
2018-01-30 19:35:03 +01:00
4a4a5fe176
tiny change
2018-01-30 19:32:22 +01:00
a45de4ec1a
FPGA tests fail if we attempt to run them in parallel
2018-01-30 19:27:22 +01:00
bb6d31a971
Merge branch 'feature/non-root' into feature/hw-testing
2018-01-30 19:26:38 +01:00
Daniel Krebs
5a7989d552
lib/memory-manager: start implementation using DirectedGraph
2018-01-30 19:16:59 +01:00
Daniel Krebs
ba7531ac46
lib/graph: allow stringifying of vertex and edge derived types
...
This yields nices debug messages and a much nice dump().
2018-01-30 19:16:59 +01:00
Daniel Krebs
22ce8f2b3f
lib/graph: slightly change interface to allow for custom edges
2018-01-30 19:16:59 +01:00
Daniel Krebs
201bbde4b6
lib/graph: move identifiers into classes
2018-01-30 19:16:59 +01:00
4f86b98fdd
add script to configure system for non-root access to FPGA
2018-01-30 19:15:45 +01:00
3047f5bb7a
vfio: only rebind pci device to VFIO driver if not already bound
2018-01-30 19:09:56 +01:00
293f496db0
pci: add function to get currently loaded kernel driver
2018-01-30 19:09:19 +01:00
269550c5dc
install libraries to fix loading of libvillas-fpga.so
2018-01-30 18:38:15 +01:00
abeaa0b077
execute FPGA unit on acs-villas
2018-01-30 18:27:13 +01:00
bd4f547e97
fix wrong tag in gitlab-ci.yml
2018-01-30 18:13:09 +01:00
c3129b35eb
use official Fedora image as base
2018-01-30 17:55:34 +01:00
1bbe0c2855
enable unit tests on CI
2018-01-30 17:54:51 +01:00
b202fa9e7d
docker: fix invalid tag name
2018-01-30 17:36:49 +01:00
Daniel Krebs
27c67f206e
lib/graph: add path-finding with loop detection and corresponding unittest
2018-01-30 17:28:42 +01:00
Daniel Krebs
ec8e9a1cd1
lib/ip-node: remove dangling function prototype
2018-01-30 15:13:23 +01:00
Daniel Krebs
7582966e16
lib: first draft of memory manager
2018-01-30 15:13:23 +01:00
Daniel Krebs
f6c02b8429
lib: add directed graph implementation incl. unittest
2018-01-30 15:13:23 +01:00
Daniel Krebs
aa33a8e028
libxil: update upstream path
2018-01-30 15:10:25 +01:00
daniel-k
f14df8aa32
lib/ip: adapt to fit new config layout provided by hwdef-parse
2018-01-23 14:47:44 +01:00
daniel-k
92aea92f19
etc: update fpga.json with output of hwdef-parse
2018-01-23 14:43:53 +01:00
daniel-k
e46720d23b
tests: improve logging
2018-01-23 14:43:30 +01:00
daniel-k
62e1a7d962
tests/fifo: fail if connecting loopback doesn't work
2018-01-23 14:43:06 +01:00
daniel-k
f642fa6428
log: provide more macros for text colors
2018-01-23 14:42:26 +01:00
daniel-k
bbff2c9a88
hwdef-parse: count total switch ports and populate property
2018-01-23 14:41:31 +01:00
daniel-k
fb37253623
hwdef-parse: populate all memory ranges based on name
...
This used to overwrite earlier memory ranges because the same was
used ('baseaddr', 'highaddr'). Now, deduce name from BASENAME and
remove prefix `C_`.
2018-01-23 14:38:12 +01:00
daniel-k
02ea98dd97
hwdef-parse: add port name
2018-01-23 12:30:54 +01:00
daniel-k
28a7f2a3ee
spdlog: fix handling of too long logger names
...
`whitespace` overflows because the result implicitly is an unsigned
value.
2018-01-23 10:09:06 +01:00
daniel-k
df93004720
scripts/hwdef-parse: include intc instance name in irq ports
2018-01-17 17:00:00 +01:00
daniel-k
935fa847aa
scripts/hwdef-parse: update ports format
2018-01-17 16:51:02 +01:00
daniel-k
4db0a98082
scripts/hwdef-parse: add memory view for each instance
2018-01-17 16:51:02 +01:00
daniel-k
f5a3c8c712
scripts/hwdef-parse: only set irqs and ports if there are any
2018-01-17 16:31:47 +01:00
daniel-k
21d1dd0a71
tests/timer: test absolute timing
2018-01-16 15:26:19 +01:00
daniel-k
61de103c9e
tests/main: assert that there's an fpga
2018-01-16 15:08:56 +01:00
