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614 commits

Author SHA1 Message Date
Niklas Eiling
5f44e16ced fpga: remove dead code and improve comments in Dino IP
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
7128da24c3 fpga: make dma able to handle sequence numbers generated in the FPGA
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
136d033cd3 fpga: fix dino setting wrong offset value to float converter
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Niklas Eiling
7991d31393 fpga/dino: add and set new registers
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-07-29 13:50:36 +02:00
Pascal Bauer
f364db1748 add parsing for baseaddress
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-29 11:29:03 +02:00
Pascal Bauer
81f8981783 add member and getter for baseaddress
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-29 11:29:03 +02:00
Pascal Bauer
54796d11b2 removed void indicator
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
80fa0429dd change name of "parseVLNV" to "parseIpIdentifier"
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
ba92d5447f add linebrakes
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
f79f7f4ca7 refactor make
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
7d37c56947 move ip initialization into function
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
05f7a03909 move configure ips into function
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
cb53713953 move reordering of ips into function
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
823ba3281e move VLNV parsing to function
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Niklas Eiling
aeda901e47 fpga: use separate locks for write and read to allow them to be used concurrently
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-05 12:30:24 +02:00
Niklas Eiling
973834b3aa fpga: use constants to access registers
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
0c3a9f4729 fpga: convert SignalType to string before printing
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
34bca6826b fpga: make dino sampling rate configurable at top level and via json
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
12af65b2b4 fpga: move register config for dino to DinoAdc
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
4911c96d8d fpga: update libxil subreport so we support 64-bit addressing
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
21221eb698 fpga: fix empty search path being an error
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
a366b80109 Fix formatting
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-05-28 19:45:55 -07:00
Niklas Eiling
ed05671a51 fpga: improve comments in register.cpp
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
c151be5cca fpga: fix includes and various comments
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
f1776f8be4 fpga: improve comments for fastRead and fastWrite
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
2cc8cad115 fpga: expose methods for finer control over DMA data path
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d fpga: improve dma latency
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
483293aec8 fpga: turn off all interrupts when using polling
this improves the latency by at least 4 us in my setup.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
57d7396c09 fpga: optimize sg descriptor rings
we are now using only one memory block for both sg rings. This is
required so that the SG interface can benefit from a read cache

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
a2d55a9b6e Harmonize descriptions of plugins
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:06:15 +02:00
e032c9857c thirdparty: Update CLI11
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
936830d484 Remove unused includes and variables
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
e7104cd039 compat: "requires" is a C++20 reserved keyword
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-03-27 17:22:07 +01:00
Niklas Eiling
a000e15308 fpga: make Dino and Aurora IPs optional in utils
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Niklas Eiling
c644c8f630 fpga: DMA: poll BD instead of hardware register
polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Niklas Eiling
ca03e1d406 fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Niklas Eiling
7f1fe8f742 fpga: default Dino rate should be 20kHz
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
Niklas Eiling
ce59e3183d fpga: fpga::createCards not finding a config is not an error
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
535d64a644 Replace last tab indentation with spaces
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
dc436073a2 Use spaces for indention of C++ comments
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
4b36073711 Use spaces for indention of CMake files
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 23:18:47 +01:00
915a6d860b Fix cppcheck performance warning
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 20:35:00 +01:00
3d73c759ea Reformat all code with clang-format
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 19:34:27 +01:00
29cf5540a0 Fix some compiler warnings in fpga code
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 19:33:40 +01:00
a2abaa3cda Merge project files, scripts and CMake files of VILLASfpga
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 19:33:23 +01:00
Niklas Eiling
542132de92 add API for createCards without std::filesystem
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 16:53:38 +01:00
Niklas Eiling
033634ac47 register: ignore strict aliasing for setting register as float
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 15:39:27 +01:00
Niklas Eiling
8a40b873be register: fix wrong fomatter declaration
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 15:11:58 +01:00
Niklas Eiling
d24a323e5c utils: remove cards from createCard
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 11:50:44 +01:00
Niklas Eiling
a3209aa344 use polling instead of interrupt
but keep interrupts for i2c

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 11:50:44 +01:00