Daniel Krebs
e66350dbf6
tests: minor fixes in logging
2018-02-14 07:28:25 +01:00
Daniel Krebs
acf273e406
tests: let them fail if no Fifo or Timer is found
2018-02-14 07:27:37 +01:00
Daniel Krebs
95e29f2706
memory-manager: allow for traversing address spaces
...
Major rework of the memory manager. Adds a memory translation class to
resolve addresses across address spaces and extents the memory manager
in order to do so.
2018-02-14 07:27:37 +01:00
Daniel Krebs
7d927155db
tests: minimal test of memory manager
2018-02-14 07:26:39 +01:00
Daniel Krebs
409340433d
enable -Wall, -Wextra and -Werror and fix new errors ( fixes #20 )
2018-02-13 16:04:34 +01:00
8206f867a5
logging: use similar log style in all modules
2018-01-31 20:24:11 +01:00
2336acaf98
tests: override some criteriod_log() functions in order to use spdlog style log output
2018-01-31 20:23:48 +01:00
51a3d0b8e9
tests: some cleanups
2018-01-31 20:22:15 +01:00
2a03d19d53
tests: readd missing graph test suite
2018-01-31 15:12:36 +01:00
b0f4577dd3
tests: automatically detect whether or not we can run tests in parallel
2018-01-31 15:12:19 +01:00
0aed1a1b12
tests: moved initialization of FPGA stuff to fpga.cpp
2018-01-31 15:11:13 +01:00
Daniel Krebs
3de2170ad6
tests: move variables to global state and set criterion jobs to 1
2018-01-31 11:17:21 +01:00
Daniel Krebs
22ce8f2b3f
lib/graph: slightly change interface to allow for custom edges
2018-01-30 19:16:59 +01:00
Daniel Krebs
27c67f206e
lib/graph: add path-finding with loop detection and corresponding unittest
2018-01-30 17:28:42 +01:00
Daniel Krebs
f6c02b8429
lib: add directed graph implementation incl. unittest
2018-01-30 15:13:23 +01:00
daniel-k
e46720d23b
tests: improve logging
2018-01-23 14:43:30 +01:00
daniel-k
62e1a7d962
tests/fifo: fail if connecting loopback doesn't work
2018-01-23 14:43:06 +01:00
daniel-k
21d1dd0a71
tests/timer: test absolute timing
2018-01-16 15:26:19 +01:00
daniel-k
61de103c9e
tests/main: assert that there's an fpga
2018-01-16 15:08:56 +01:00
daniel-k
16455bdd13
tests/fifo: cleanup
2018-01-16 15:08:27 +01:00
daniel-k
e626abfb52
tests/timer: add basic timer test
2018-01-16 15:08:12 +01:00
daniel-k
3cf50db98d
logging: use new spdlog library in favor of Logger
2018-01-10 15:49:53 +01:00
daniel-k
71a54eeab6
lib/ips: implement fifo driver and adapt test
2018-01-10 11:02:08 +01:00
daniel-k
018c89a2b0
tests/main: C++-ify
2018-01-10 11:02:08 +01:00
daniel-k
a5b5e317d4
wip implementing dependency parsing and proper memeory handling
...
works and compiles so for. next is to implement different IP interfaces
(Model, Interface, DataMover, Infrastructure, ...)
2018-01-10 11:02:08 +01:00
daniel-k
e590d1a350
add namespace villas::fpga and villas::fpga::ip and some renaming
2018-01-10 11:02:08 +01:00
daniel-k
b0e55e6fb2
current wip implementing card, many changes in ip too
2018-01-10 11:02:08 +01:00
daniel-k
d63c2b30bf
tests: compile main as C++
2018-01-10 11:02:08 +01:00
daniel-k
737a5851df
lib/card: start FPGA card prior to parsing
...
Initializing IPs may want to probe the actual hardware for feature
detection (e.g. DMA), so the card has to be started in order to access
any memory on the card.
2017-11-28 11:26:41 +01:00
daniel-k
d67a120902
tests/dma: fix chunk size for simple DMA (should have been 4k)
2017-11-22 19:47:04 +01:00
daniel-k
c67c8aac5b
tests: add fpga.json and correctly parse it for unit tests
2017-11-22 19:46:07 +01:00
c3164e93ef
imported source code from VILLASfpga repo and made it compile
2017-11-21 21:31:08 +01:00
