Few IP parameters exported in smaller cases to the hdf
but the dirver tcl is checking for the same parameters in
upper case resulting wrong values are being genearted
in xparameters.h file. This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Created a new vesrion of can can_v3_1
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Video PHY driver for abstraction of GTs.
Contribution from Gilbert Magnaye on HDMI.
Contribution from Vamsi Krishna Dhanikonda on DisplayPort.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Rohit Consul <rohitco@xilinx.com>
Compilation failure if an HDCP design was generated without a
timer counter instatiated.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
PHY ready check is now done immediately before initiating link
training.
In pass-through designs where the TX reference clock is derived
from the input RX clock, having no RX clock would have resulted
the TX initialization failing due to PHY ready time out.
This patch allows TX and RX to both be initialized in any
order.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
For sst flash parts we need to unlock global protection bits and use
bulk erase command instead of chip erase.This patch updates the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
For sst flash parts we need to unlock global protection bits and use
bulk erase command instead of chip erase.This patch updates the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Set speed of 1G for silicon only and run at 100Mbps on emulation platforms.
CRL_APB register configuration to 1000Mbps is also only required for silicon.
Minor comment corrections done.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Different GEM instances are present on evaluation and emulation platforms
of Zynq Ultrascale+ MPSoC.
To allow for automatic testing, select XPS_GEMx_INTR_ID based on the
PSU_<> present. Left initial definition intact for Zynq.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch adds HDCP example and modifies examples, readme, index
files.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
This patch adds HDCP example and modifies examples, index, readme files.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
This patch integrates HDCP and Timer in DisplayPort Receiver Subsystem.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei Simion <andreis@xilinx.com>
Increase the setup and hold time of qspi to accomodate for a worst case
of ~15ns with ref clk of 300MHz.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This patch adds custom resolution support and wrapper function
for setting a redriver path.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Acked-by: Andrei-Liviu Simion <andreis@xilinx.com>
Fixed the read API for video lock monitor to read from
peripheral. Update example design to align with example design
update in hw
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Parts of the driver check whether or not the function pointers are
set and call appropriate callbacks if they are.
Ensure function pointers are set to 0 / NULL during configuration
initialization.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
When the MSA is updated, provide a mechanism to run a user-defined
callback instead of using the MSA values from the driver's
structure.
This is useful if another DP core exists in the system (RX). Using
the new callback mechanism, the user can specify to use whatever
MSA values exist in the RX core as the values to transmit.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
Expose the AXI bus clock frequency to the higher-level.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
A driver may be included even when there is no associated core
present. (See the DEPENDS option in data/*.mdd).
If another driver includes this TmrCtr driver, despite no
associated timer counter core existing, then xtmrctr.tcl won't be
invoked by SDK and the xtmrctr_g.c will not be generated.
If this file is not generated, the BSP will include the default
xtmrctr_g.c which was previously assuming that there is at least
one instance of the core in the system.
Also, the XPAR_XTMRCTR_NUM_INSTANCES wasn't being defined in this
case.
Protection against such a scenario is required.
Some subsystem drivers will include all subcore drivers,
regardless whether they are a part of the system or not.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
Some subsystem drivers have dependencies on all subcore drivers.
If no subcore of that type is present, the HDCP subcore driver's
TCL file won't be executing, and the XPAR_XHDCP_NUM_INSTANCES
will remain undefined.
This will cause a compilation error due to XHdcp1x_LookupConfig
using this definition.
This patch protects against such a scenario.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
The configuration initialization function is now consistent with
other drivers.
Added effective address as an argument to CfgInitialize.
This is necessary when memory addresses are translated differently
from the physical base address and for subsystem drivers whose
subcore base addresses appear as relative offsets to the base
address of the subsystem.
Moved configuration related content from LookupConfig to
CfgInitialize.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
Driver has been renamed to XV_Hdmi* rather than XHdmi*.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
To prevent unexpected behavior resulting from jumping to a NULL
address.
Previously, if the user didn't define a callback before the
occurence of an interrupt, the driver's interrupt handler would have
invoked a function pointer to NULL.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
Added configuration initialization and hardware initialization API
functions.
The XTmrCtr driver is now consistent with other drivers.
The previous initialization structure disallowed using a different
base address from what was found in the xparameters and the
configuration table of the core.
The XTmrCtr_Initialize function was overriding the effective base
address internal to the core - it still as to keep the API
functionality intact for backward-compatibility.
Internally, the function is calling the new APIs.
This poses an issue if the memory addresses have been translated
differently from the physical base address.
Also, such as is for subsystem drivers, the base address of one
of the subsystem's subcores will appear as a relative offset to
the base address of the subsystem.
This issue is addressed by providing the higher level with control
of which base address will be used by the driver.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
The status and mask registers are independent - the interrupt status
is not affected by the software controlled interrupt mask register.
For the contents of the interrupt mask to take effect, qualification
of the interrupt status needs to happen in software.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
This patch adds support for ICC ARM Compiler by
removing __inline keyword in case of IAR compiler.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
Acked-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Modify clock config function to move all ZynqMP GEM related code inside
XPAR_<psu ethernet ip> checks. This fixes the compilation errors for Zynq
that are caused by references to GEM2/3.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Corrected VsyncStart and also corrected register
read to XVTC_DVSYNC_F1_OFFSET in XVtc_GetDetector API
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Write to CRL_APB registers for clock control and enable 1G speed.
Move clock configuration to a separate function.
Update payload to jumbo size.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Read the phy idetifier register to identify whether PHY is Marvell or TI.
Add support for TI PHY sequence by writing to PHY CNTRL register and
tuning using RGMIICTL/RGMIIDCTL registers.
Access to extended registers in TI pHY is through REGCR and ADDAR registers.
ADDAR should be used to write the offset of register to be written
and then the value to be written. REGCR should indicate when ADDAR contains
register offset and when it contains register data.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
