Harini Katakam 2b3a7c5e4c qspipsu: Switch to I/O mode before clearing RX FIFO ... There is a bug wherein the DMA listening to RX empty status goes busy if RX FIFO clear bit is set in the FIFO control register, even if there is no transfer request. So switch to I/O mode always to clear RX FIFO and restore the mode in the end. Signed-off-by: Harini Katakam <harinik@xilinx.com>		2015-03-19 13:55:46 +05:30
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data	qspipsu_v1_0: Removed unnecessary puts in tcl.	2015-02-19 18:41:50 +05:30
examples	qspipsu_v1_0: Modified the file permissions.	2015-02-19 17:56:40 +05:30
src	qspipsu: Switch to I/O mode before clearing RX FIFO	2015-03-19 13:55:46 +05:30