2b3a7c5e4c
There is a bug wherein the DMA listening to RX empty status goes busy if RX FIFO clear bit is set in the FIFO control register, even if there is no transfer request. So switch to I/O mode always to clear RX FIFO and restore the mode in the end. Signed-off-by: Harini Katakam <harinik@xilinx.com> |
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| .. | ||
| Makefile | ||
| xqspipsu.c | ||
| xqspipsu.h | ||
| xqspipsu_g.c | ||
| xqspipsu_hw.h | ||
| xqspipsu_options.c | ||
| xqspipsu_sinit.c | ||