embeddedsw/XilinxProcessorIPLib/drivers/vprocss/examples/src
Rohit Consul cf3ea2ed03 vprocss: Add 2 sec wait to example design source files
VTC in example design has switched to a slower 9MHz clock.This
essentially provides < 2fps frame rate. Vidout needs 3-4 frames
to acquire lock. After vpss configuration wait for 2 sec (mb_sleep)
before checking for vidout lock

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-09-15 18:47:40 +05:30
..
lscript.ld vprocss: Add xsct tck script to automate sdk project creation 2015-09-04 11:03:32 +05:30
main.c vprocss: Add 2 sec wait to example design source files 2015-09-15 18:47:40 +05:30
periph.c vprocss: Add xsct tck script to automate sdk project creation 2015-09-04 11:03:32 +05:30
periph.h vprocss: Add xsct tck script to automate sdk project creation 2015-09-04 11:03:32 +05:30
system.c vprocss example: MIG instance name changed in example design 2015-09-04 11:04:31 +05:30
system.h vprocss: Add xsct tck script to automate sdk project creation 2015-09-04 11:03:32 +05:30