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3161 commits 1 branch 6 tags 8.6 MiB
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146 commits

Author SHA1 Message Date
Clifford Wolf
bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf
8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf
76352c99c9 Added "prep -nokeepdc" 2016-09-30 17:02:52 +02:00
Clifford Wolf
2ee9bf10d0 Added "prep -nomem" 2016-08-30 23:57:24 +02:00
Clifford Wolf
6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf
d77a914683 Added "wreduce -memx" 2016-08-20 12:52:50 +02:00
Clifford Wolf
15ef608453 Added memory_memx pass, "memory -memx", and "prep -memx" 2016-08-19 19:48:26 +02:00
Clifford Wolf
4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf
5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf
cdb58f68ab Added "prep -auto-top" and "synth -auto-top" 2016-07-11 11:40:55 +02:00
Clifford Wolf
95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf
52b0b4e31e Do not run "wreduce" in "prep -ifx" 2016-06-08 12:14:32 +02:00
Clifford Wolf
2032e6d8e4 Added "proc_mux -ifx" 2016-06-06 17:15:50 +02:00
Clifford Wolf
09ffebb995 Added "prep -flatten" and "synth -flatten" 2016-04-24 00:48:33 +02:00
Clifford Wolf
77aa2031e7 Converted "prep" to ScriptPass 2016-04-24 00:48:06 +02:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
2553319081 Added ScriptPass helper class for script-like passes 2016-03-31 11:16:34 +02:00
Clifford Wolf
1d0f0d668a Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
Clifford Wolf
19c20235b5 Added more cell help messages 2016-03-29 15:14:43 +02:00
Clifford Wolf
bd10927f45 Progress in cell library documentation 2016-02-01 13:58:10 +01:00
Clifford Wolf
f1b959dc69 Run opt_const before check in default scripts 2015-12-22 11:15:05 +01:00
Clifford Wolf
bbcbf739e6 Progress on cell help messages 2015-10-20 16:49:11 +02:00
Clifford Wolf
5d1c0ce7c0 Progress on cell help messages 2015-10-17 02:35:19 +02:00
Clifford Wolf
25c1f6e605 Added "prep" command 2015-10-14 22:46:41 +02:00
Clifford Wolf
87adb523aa Added more cell descriptions 2015-10-14 20:30:59 +02:00
Clifford Wolf
7d3a3a3173 Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Clifford Wolf
924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf
d5b1a90b33 Added $tribuf and $_TBUF_ sim models 2015-08-16 13:05:32 +02:00
Clifford Wolf
ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Larry Doolittle
6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf
e4ef000b70 Adjust makefiles to work with out-of-tree builds 
This is based on work done by Larry Doolittle
 2015-08-12 15:04:44 +02:00
Clifford Wolf
8d6d5c30d9 Added WORDS parameter to $meminit 2015-07-31 10:40:09 +02:00
Clifford Wolf
f0c9a099d2 Added "synth -nofsm" 2015-07-02 15:25:38 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
ed128b82d7 Added "synth -nordff -noalumacc" 2015-06-15 17:07:40 +02:00
Clifford Wolf
794d22969d Added simplemap $lut support 2015-04-27 10:16:07 +02:00
Clifford Wolf
95944eb69e make all vector-size related integer params in $mem sim model signed 
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
 2015-04-05 17:26:53 +02:00
Clifford Wolf
706631225e Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types 2015-04-05 09:45:14 +02:00
Clifford Wolf
b005eedf36 Added $assume cell type 2015-02-26 18:04:10 +01:00
Clifford Wolf
4d34d031f9 Added "stat" to "synth" and "synth_xilinx" 2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9 Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
Clifford Wolf
ec05242c27 Smaller default parameters in $mem simlib model 2015-02-15 00:20:05 +01:00
Clifford Wolf
dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf
04cb947d6a Added "check" command 2015-02-13 14:34:51 +01:00