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645 commits

Author SHA1 Message Date
8a6832edc3 card: allow loading IPs devicetree from extra file 2022-08-30 12:21:46 -04:00
0597e975a0 update gitignore 2022-08-30 12:21:46 -04:00
a433ba5d44 add VSCode configuration for GDB debugging as root 2022-08-30 12:21:46 -04:00
f2a1c78f96 harmonize logger names 2022-08-30 12:21:45 -04:00
bcec3efd5f update code to latest common submodule 2022-08-30 12:21:45 -04:00
28262ef79b remove old configs 2022-08-30 12:21:45 -04:00
b202f11d05 update hardware submodule 2022-08-30 12:21:45 -04:00
7e3a58ce2e update gitignore 2022-08-30 16:36:01 +02:00
8beac4a394 fix CI 2022-03-04 03:46:47 -05:00
c90b1c1f3e fix format strings 2022-03-04 03:33:47 -05:00
8a99307ba2 update config include 2022-03-04 03:33:27 -05:00
49572d0a74 adapt to new plugin registry 2022-03-04 03:33:07 -05:00
53c4c4bf77 remove obsolete htdocs setting 2022-03-04 03:30:42 -05:00
8d6e9eda5d remove hardware submodule 2021-07-07 12:31:33 +02:00
f59a763cd1 Merge branch 'fix-cmake' into 'master'
cmake: allow linking libxil from non-standard location

See merge request acs/public/villas/fpga/fpga!15
2020-11-12 00:45:06 +01:00
2bbe5bc0ab cmake: allow linking libxil from non-standard location 2020-11-12 00:19:55 +01:00
a04c1d7abf ci: add cppcheck 2020-09-21 09:37:10 +02:00
5502d3577b remove unused submodules 2020-08-17 17:21:18 +02:00
8ec16094f2 fix code-style 2020-07-27 16:48:53 +02:00
e5545aa17e emc: add initial code to flash FPGA bitstream via PCIe 2020-07-08 17:16:43 +02:00
eabae63714 update submodules 2020-07-08 15:24:01 +02:00
08114652d6 emc: add stub IP 2020-07-08 15:20:05 +02:00
10b8878279 fix naming of factories 2020-07-08 15:10:26 +02:00
8bb033f89d update hardware submodule and move hwdef-parse script into hardware repo 2020-07-08 14:14:38 +02:00
Hatim Kanchwala
8a4e95d75c Use sensible colour scheme for error status output 2020-07-04 15:11:01 +02:00
Hatim Kanchwala
89f75c9a57 Remove old JSON config files 2020-07-04 15:11:00 +02:00
c4fe7e4b07 update libxil submodule 2020-06-15 22:49:43 +02:00
ba9d670d4b cmake: make unit-tests optional 2020-06-15 22:49:19 +02:00
7e2365bfa0 ci: update CI config 2020-06-15 22:09:18 +02:00
031311ba95 docker: add missing deps 2020-06-15 21:45:50 +02:00
a935a5856a docker: add mising ssl headers 2020-06-15 21:29:46 +02:00
2700493f2f docker: fix location of FEIN e.V. repo 2020-06-15 21:25:55 +02:00
c5e3d3dd4a node: add connect() with reverse path 2020-06-15 21:21:16 +02:00
6c225c8fae update VILLAScommon submodule 2020-06-15 21:21:05 +02:00
74f55fa98c refactor: more code-style improvements 2020-06-15 21:08:49 +02:00
cc456b6525 refactor: no namespace scopes in source files 2020-06-14 22:12:41 +02:00
d938bd95b1 cmake: fixups for inclusion into VILLASnode 2020-06-14 22:11:58 +02:00
a9f9dc4a37 refactor: no namespace scoeps in source files 2020-06-14 22:11:26 +02:00
8b7bbe27c6 refactor: whitespaces for references 2020-06-14 22:03:50 +02:00
e86a291dfd update VILLAScommon submodule 2020-06-12 00:08:04 +02:00
6b3164dd26 refactor IpNode and IpCore class names 2020-06-12 00:05:03 +02:00
7c92a30ab4 several cleanups and bugfixes 2020-06-11 23:55:05 +02:00
bb8a711f02 use new getter for graph 2020-06-11 23:40:12 +02:00
1af96b20e4 pipe: use correct DMA instance 2020-06-11 19:02:49 +02:00
b7e5bfead2 harmonize codestyle 2020-06-11 18:38:46 +02:00
3f1ab8e862 use new vlnv id for aurora_axis 2020-06-11 18:19:28 +02:00
77b55f65f7 use new plugin mechanism 2020-06-11 18:19:03 +02:00
91f9000038 unit-tests: allow FPGA configuration to provided via env var 2020-06-11 16:09:58 +02:00
cc1d1d4298 plugin: fix lookup 2020-06-11 16:01:42 +02:00
86f8997b05 gpio: add new IP for AXI programmable GPIO 2020-06-11 15:58:02 +02:00