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6254 commits 171 branches 31 tags 76 MiB
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65 commits

Author SHA1 Message Date
Niklas Eiling
7e1bad3590 fpga: Use float accessor for reading and writing floats 
This fixes breaking strict aliasing rules.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-26 10:09:01 +02:00
Niklas Eiling
36687d6af4 fpga: fix debug output 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-26 10:09:01 +02:00
Niklas Eiling
b52f445a52 fpga: handle receving more data than size of configured signals 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-26 10:09:01 +02:00
Niklas Eiling
9b79c16fb3 fpga: make FPGA support sending and receiving integers 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-08-26 10:09:01 +02:00
Niklas Eiling
7128da24c3 fpga: make dma able to handle sequence numbers generated in the FPGA 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
d2c1f55f21 fpga: fix timestep being hardcoded 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
675c489126 fpga: switch to float accessor for writes 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-07-29 13:50:36 +02:00
Niklas Eiling
f84e0691f1 fpga: fix redundant return in getPollFD 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-06-06 09:29:29 +02:00
Niklas Eiling
7ef44a4911 fpga: do not return poll FDs if we are not using FDs 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-06-06 09:29:29 +02:00
Niklas Eiling
584712300d fpga: fix wrong unpack string for config parsing 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-06-06 09:29:29 +02:00
Niklas Eiling
50bc9d9510 fpga: use snake case for low_latency_mode 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
296b7d873a fpga: improve comments and removed dead code 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
b74ebd391f fpga: remove output from performance critical code 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
0c3a9f4729 fpga: convert SignalType to string before printing 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
34bca6826b fpga: make dino sampling rate configurable at top level and via json 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
f1776f8be4 fpga: improve comments for fastRead and fastWrite 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
a2ff0aca43 fix formatting in fpga 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
9cf926d84e fpga: add lowLatencyMode setting 
This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d fpga: improve dma latency 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Steffen Vogel
2529c7b2d7 Remove superfluous includes 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-04-10 18:56:28 +02:00
Niklas Eiling
c644c8f630 fpga: DMA: poll BD instead of hardware register 
polling HW is slow (>1us). Polling RAM is faster. This is a first implementation which only polls the first BD that is active. This is why this commit also removes the second read in nodes/fpga. This is not really useful anyways.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-03-14 16:07:45 +01:00
Niklas Eiling
322cdf9639 fpga: do not create the vfio container twice 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-03-14 16:07:45 +01:00
Niklas Eiling
49523a5076 fpga: remove std::filesystem and properly retrieve searchPath from 
configPath

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-27 13:40:12 +01:00
Niklas Eiling
ea0bfcf7f4 fpga: clean up debug outputs 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-27 13:40:12 +01:00
Niklas Eiling
26e22ca6f4 fpga: make implementation compatible with new createCard interface 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-27 13:40:12 +01:00
Niklas Eiling
47362ccede fpga: enable inline config of card 
additionally to configuring the card in a separate block, we need to be
able to configure the card from the node config to enable libvillas
users to use the fpga node-type.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-27 13:40:12 +01:00
Steffen Vogel
226ccecd19 Remove usage of std::filesystem 
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2024-02-26 17:10:57 +01:00
Niklas Eiling
4ca9c88bd0 fpga: add note about wrong cast 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-08 11:19:51 +01:00
Niklas Eiling
97a391c271 update fpga submodule 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-08 11:19:51 +01:00
Niklas Eiling
18aa0c8862 rework fpga node type 
The various changes in fpga require a rewrite of the fpga node type.
To allow relative paths for the fpga config file, Config and SuperNode
had to be modified so they store the path of the main config file.
The syntax of the fpga node type configuration has changed - the example
config in etc has been modified accordingly.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-08 11:19:51 +01:00
Steffen Vogel
02a2aa4f94 Apply clang-format changes 
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-09-08 11:37:42 +02:00
Steffen Vogel
68654f95f2 Add periods after file headers and fix email addresses 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-09-07 11:16:04 +02:00
Steffen Vogel
0735eb0f89 Make project REUSE compliant 
And various other cleanups and harmonizations

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-09-07 11:16:04 +02:00
Niklas Eiling
554515fe30 fix fpga node type to work with current fpga master 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-07-25 18:16:51 +02:00
Philipp Jungkamp
f73efabd18 Adapt fpga node to changed uuid passing 
Signed-off-by: Philipp Jungkamp <Philipp.Jungkamp@opal-rt.com>
 2023-06-30 11:30:05 +02:00
Steffen Vogel
7749a3a922 No not pass super-node UUID to Node::parse() any longer 
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-06-30 10:51:01 +02:00
Steffen Vogel
d57a5d3306 Refactor parameter name for parse() from cfg to json 
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-06-30 10:48:43 +02:00
Steffen Vogel
a37b64111f fpga: call base-class function for NodeFactory::start() 
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-06-21 11:48:04 +02:00
Steffen Vogel
f6789e4739 fix broken VILLASfpga node-type 
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-01-13 11:28:53 +01:00
Manuel Pitz
c4bce72c04 make compatible to fmt version 9.0.3 
Signed-off-by: Manuel Pitz <manuel.pitz@eonerc.rwth-aachen.de>
 2023-01-11 12:11:57 +01:00
Steffen Vogel
7d982e12b3 fpga: fix cppcheck warnings 
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-01-10 16:31:01 +00:00
Steffen Vogel
5398006734 fpga: fix creation of VFIO container 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:10:02 +01:00
Steffen Vogel
3b5f686262 code-style fixes 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:10:02 +01:00
Steffen Vogel
ae17d58cc4 fpga: remove unused code 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:10:02 +01:00
Steffen Vogel
1c7d57d5f5 fpga: do not reset VFIO container by hand 
We can rely on the Dtor of the global shared_ptr to destruct the container

Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:10:02 +01:00
Steffen Vogel
20ffee08e4 fpga: improve code style 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:10:02 +01:00
Steffen Vogel
9a4f8a0b19 fpga: first compiling version 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:09:35 +01:00
Steffen Vogel
de9bda4d74 fpga: fix syntax errors 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2023-01-09 11:09:35 +01:00
Steffen Vogel
7eec1bb753 update Steffens mail address 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2022-12-16 23:44:07 +01:00
Steffen Vogel
b94746effb relicense VILLASnode to Apache 2.0 2022-07-04 18:23:57 +02:00