Hatim Kanchwala
73e85f2e5a
Add intial header file for Aurora
2020-05-26 14:46:35 +02:00
f6a78bea69
dma: add dump() method
2019-08-15 13:54:58 +02:00
Hatim Kanchwala
bf74db8e79
Debug update
2019-06-24 12:11:44 -04:00
2112038d70
Merge branch 'feature/hls-rtds2gpu' into develop
2018-08-21 13:51:32 +02:00
76b1695586
move more code to VILLAScommon repo
2018-08-21 13:27:04 +02:00
df89b63368
fix include paths
2018-08-21 11:07:53 +02:00
de566d441d
move common code to VILLAScommon submodule
2018-08-21 01:14:18 +02:00
Daniel Krebs
b2698c8bd5
rtds2gpu: update register type to work for more complex payloads
2018-07-26 16:49:06 +02:00
Daniel Krebs
26abf44d2f
villas/memory: add sanity check to deny allocating zero-sized memory
2018-07-20 16:50:54 +02:00
Daniel Krebs
375b6b5cd3
common/memory: let allocators own a memory block
...
This is useful when we sub-delegate management of a memory block
to another allocator.
2018-07-20 16:44:50 +02:00
Daniel Krebs
0cdc05c3d5
rtds2gpu: add struct for memory layout of rtds2gpu buffer
2018-07-11 16:06:48 +02:00
7409d2024d
add more copyright / license headers
2018-06-25 17:03:09 +02:00
7fd6599ea6
update copyright years
2018-06-25 15:33:14 +02:00
Daniel Krebs
d853d5e0d3
wip GPU RTT
2018-06-06 09:55:14 +02:00
Daniel Krebs
49f0c2e0c4
unit test RTT via CPU to/from RTDS works!
2018-06-04 19:06:36 +02:00
Daniel Krebs
92bfe849b4
ips/rtds2gpu: use new connect interface
2018-06-04 17:36:36 +02:00
Daniel Krebs
f413712b86
gpu2rtds: unit test working
2018-06-04 17:36:36 +02:00
Daniel Krebs
010e0c3681
hls: add base HLS IP and enable virtual multi-inheritance
...
Virtual inheritance is required because (for example) the Rtds2Gpu
IP inherits from Hls and IpNode who both inherit from IpCore.
2018-06-04 17:36:36 +02:00
Daniel Krebs
5c67dc3727
rtds2gpu: update vlnv to match v1.1 and adapt config to new bitstream
2018-06-04 17:36:15 +02:00
Daniel Krebs
28458fdf8a
update rtds2gpu HLS IP to v1.1
...
- better tested IP (testbenches)
- detect invalid frame sizes
- more status reporting
2018-06-04 17:36:15 +02:00
Daniel Krebs
bf286568dd
rtds2gpu IP works
2018-06-04 17:36:15 +02:00
Daniel Krebs
47bd186f5e
ip-node: move stream graph to IpNode and add easy-to-use connect interface
2018-06-04 17:31:12 +02:00
Daniel Krebs
28143e7188
ips/rtds: add C++ version of RTDS IP
2018-06-04 14:20:06 +02:00
Daniel Krebs
a93278b74e
ips/dma: expose names of its treaming ports
2018-06-04 14:20:06 +02:00
Daniel Krebs
8e63785073
ips/dma: change interface, get byte count from {read,write}Complete()
2018-06-04 14:20:06 +02:00
Daniel Krebs
7479675361
ips/intc: remove unused code
2018-06-04 14:20:06 +02:00
Daniel Krebs
2e339b406d
lib/ips: add data fifo IP needed for stream routing
2018-06-04 14:20:06 +02:00
Daniel Krebs
a0c5acce4c
ip-node: implement connect interface and update AxiStreamSwitch implementation
2018-06-04 14:20:06 +02:00
Daniel Krebs
a1daf95202
lib/card: lookup IP by identifier
2018-06-04 14:20:06 +02:00
Daniel Krebs
967e39e36c
ip-node: add implementation of StreamGraph for automatic routing
2018-06-04 14:20:06 +02:00
Daniel Krebs
5097827757
fix include paths, use <villas/...> style
2018-06-04 13:24:57 +02:00
Daniel Krebs
c15189b74b
common/memory: implement freeing for LinearAllocator
...
This is still very simple. Only really free memory, when all allocation
have been deallocated so we only need to keep track of the current
number of allocations.
2018-05-16 11:27:03 +02:00
Daniel Krebs
13fd3f3c2a
gpu: implement basic GPU plugin that can do DMA to and from its memory
...
Using CUDA, memory can be allocated on the GPU and shared to peers on
the PCIe bus such as the FPGA. Furthermore, the DMA on the GPU can also
be used to read and write to/from other memory on the PCIe bus, such as
BRAM on the FPGA.
2018-05-15 18:15:17 +02:00
Daniel Krebs
7dcdfaccd9
ips/dma: let user deal with making memory accessible to DMA
...
It is probably too costly to do (and verify) it on every read
or write. Furthermore, the user knows better how to make a certain
memory available to the DMA.
2018-05-15 18:04:24 +02:00
Daniel Krebs
89b5169a6e
ips/pcie: parse AXI/PCI BARs and create mappings to/from PCIe address space
...
This is used for translations that don't use VFIO which used to bridge
the PCIe address space by creating direct mappings from process VA to
the FPGA. When we want to communicate directly via PCIe without the
involvment of the CPU/VFIO, we need the proper translations that are
configured in the FPGA hardware.
2018-05-15 18:04:24 +02:00
Daniel Krebs
364b137156
fpga/card: make pci device a class member (needed later)
2018-05-15 18:04:24 +02:00
Daniel Krebs
8f3833bc73
ips/dma: rename pingpong to memcpy and always connect loopback
2018-05-15 18:04:24 +02:00
Daniel Krebs
ad820a3618
kernel/pci: parse BAR regions
2018-05-15 18:04:24 +02:00
Daniel Krebs
2bfb9e2450
common/memory: expose method to dump memory graph to file
2018-05-15 18:04:24 +02:00
Daniel Krebs
e819829560
directed-graph: add dumping to dot-file (graphviz)
2018-05-15 18:04:24 +02:00
Daniel Krebs
1b2e7d312e
common/memory: add host DMA memory allocator using udmabuf
2018-05-15 18:04:24 +02:00
Daniel Krebs
6b7d694103
common/BaseAllocator: test allocated memory for accessibility
...
Write to and read-verify allocated memory block when using allocate()
wrapper.
2018-05-15 18:04:24 +02:00
Daniel Krebs
2477ed4b4b
common/memory: provide getPciAddressSpace() for a common PCIe address space
2018-05-15 18:04:24 +02:00
Daniel Krebs
1470490747
common/memory: provide findPath() to get a path of address spaces
2018-05-15 18:04:24 +02:00
Daniel Krebs
cea353aa7f
directed-graph: add getters for vertices of an edge
2018-05-15 18:04:24 +02:00
Daniel Krebs
105f47d2d0
common/memory: add check-callback to getPath() to select desired path
...
This is a workaround until we have a better heuristic (maybe shortest
path?) to choose between multiple paths in the graph. Since the (abstract)
graph has no idea about memory translations, getPath() may even yield
paths that are no valid translation because a pair of inbound/outbound
edges must not neccessarily share a common address window, but from the
perspective of the abstract graph present a valid path.
The callback function is used by the MemoryManager to verify if a path
candidate represents a valid translation.
2018-05-15 18:04:24 +02:00
Daniel Krebs
29709aed7a
directed-graph: make compile with C++11 (no C++17 with CUDA)
2018-05-15 18:04:24 +02:00
Daniel Krebs
9490594167
allocator: properly remove memory block from memory graph
2018-05-15 18:04:24 +02:00
Daniel Krebs
80386d1085
vfio: correctly set container on group
2018-05-15 18:04:24 +02:00
Daniel Krebs
b6ff452e53
vfio: minor refactoring
2018-05-15 18:04:24 +02:00
