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6203 commits 171 branches 31 tags 76 MiB
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280 commits

Author SHA1 Message Date
Pascal Bauer
81f8981783 add member and getter for baseaddress 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2024-07-29 11:29:03 +02:00
Pascal Bauer
80fa0429dd change name of "parseVLNV" to "parseIpIdentifier" 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2024-06-27 09:54:58 +02:00
Pascal Bauer
7d37c56947 move ip initialization into function 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2024-06-27 09:54:58 +02:00
Pascal Bauer
05f7a03909 move configure ips into function 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2024-06-27 09:54:58 +02:00
Pascal Bauer
cb53713953 move reordering of ips into function 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2024-06-27 09:54:58 +02:00
Pascal Bauer
823ba3281e move VLNV parsing to function 
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
 2024-06-27 09:54:58 +02:00
Niklas Eiling
aeda901e47 fpga: use separate locks for write and read to allow them to be used concurrently 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-06-05 12:30:24 +02:00
Niklas Eiling
12af65b2b4 fpga: move register config for dino to DinoAdc 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-05-29 09:18:00 +02:00
Niklas Eiling
c151be5cca fpga: fix includes and various comments 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
f1776f8be4 fpga: improve comments for fastRead and fastWrite 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
2cc8cad115 fpga: expose methods for finer control over DMA data path 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d fpga: improve dma latency 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Niklas Eiling
57d7396c09 fpga: optimize sg descriptor rings 
we are now using only one memory block for both sg rings. This is
required so that the SG interface can benefit from a read cache

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-04-19 10:09:47 +02:00
Steffen Vogel
a2d55a9b6e Harmonize descriptions of plugins 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-04-10 09:06:15 +02:00
Niklas Eiling
ca03e1d406 fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-03-14 16:07:45 +01:00
Steffen Vogel
3d73c759ea Reformat all code with clang-format 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-02-29 19:34:27 +01:00
Steffen Vogel
29cf5540a0 Fix some compiler warnings in fpga code 
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
 2024-02-29 19:33:40 +01:00
Niklas Eiling
542132de92 add API for createCards without std::filesystem 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 16:53:38 +01:00
Niklas Eiling
8a40b873be register: fix wrong fomatter declaration 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 15:11:58 +01:00
Niklas Eiling
d24a323e5c utils: remove cards from createCard 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 11:50:44 +01:00
Niklas Eiling
fb742dddd1 register: increase register num to 8 
the VHDL changed so we need to change register here too

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 11:50:44 +01:00
Niklas Eiling
4b7ed781c0 card: add API to create a single card 
this is a preparation for allowing defining the card in the node config
rather than separately.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-26 11:50:44 +01:00
Niklas Eiling
d54e4eb3f0 ips/register: add IP for the new register interface 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-14 14:20:33 +01:00
Niklas Eiling
c730412e98 ips/intc: move deinit to stop instead of destructor 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-14 14:20:33 +01:00
Niklas Eiling
2c72af935a ips/i2c: move deinit to stop instead of destructor 
accessing register space from destructor can cause use after free errors

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-14 14:20:33 +01:00
Niklas Eiling
f2db38fe44 ip/switch: reformat and add function that prints current switch config 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
7c6d350eb0 format and increase robustness of interuppt handling 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
edb996ebfd add fmt::formatter for Dino::IoextPorts 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-02-07 18:21:45 +01:00
Niklas Eiling
b2fcfeaa67 move more of the switch configuration boilerplate into ConnectString 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-12 11:46:59 +01:00
Niklas Eiling
ca6c70e09b ConnectString: Make channel data type more generic 
we can not only connect Aurora channels to the switch so use Node
instead as the data type

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-12 11:46:59 +01:00
Niklas Eiling
8b95182b08 automatically configure and test Dino based on hwdef json 
this currently requires manually adding the mapping of Dinos to i2c
buses in the fpga json.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
b5682290c2 I2c: use Switch::selfTest to check i2c bus 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
db062f08bd Dino: overload operator>> for IoextPorts 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
60c65c2880 verify more assumptions in i2c 
add selftest to I2c and readback Dino configuration to verify it was
actually set

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
335dd2c0ce fix bug where Dino IP always read 0 from i2c. Add hardware mutex to I2c 
and to I2c::Switch

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
acaa4dd9de improve i2c IP 
more code reuse, add function for reading from a register i.e. combined
write and read

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
dbe4e4e472 add i2c configuration logic to dino IP 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
810b1259f8 fix double start of i2c bus driver and move channel map to header 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
48846ace39 i2c: add handling of BusNotBusy interrupt on reads. add retrying of 
channel reads in case inconsistent state was detected.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
57177c074e fix several issues with i2c implementation and add support for 
interacting with i2c switches

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
1578a26915 i2c: fix missing getMemoryBlocks method leading to unmapped memory 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
7e07da6e60 add i2c ip draft 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2024-01-09 17:14:05 +01:00
Niklas Eiling
d61337023e add draft for i2c drvier implementation 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-13 15:17:26 +01:00
Niklas Eiling
2967fb8ac9 fix fpga.cpp unit test failing due to changed DeviceList interface 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Niklas Eiling
654ee84e9e make FPGA device interface agnostic 
remove explicit mentioning of PCIe in the use of Device as a preparation
for integrating platform devices. auto formatted some files.

Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-12-12 14:08:34 +01:00
Philipp Jungkamp
e2c2ec2c8b Fix fmt 10.0.0 related formatting errors. 
Signed-off-by: Philipp Jungkamp <p.jungkamp@gmx.net>
 2023-09-26 17:00:31 +02:00
Steffen Vogel
157d5b21d7 Make REUSE copyright notice the same as in other VILLASframework projects and fix comments (#82) 
This edits the headers in every file so the copyright notice mentions RWTH Aachen University. We also update some copyright years and fix various comments so the header is the same across all of VILLASframework.

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

* Harmonize comment and code-style

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>

---------

Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
 2023-09-08 11:35:18 +02:00
Niklas Eiling
d9993409e0 fix possible NULL dereferencing in villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 14:56:54 +01:00
Niklas Eiling
9d4cd5384d clean up debuggin output and fix scanf usage in villasfpga_dma.c 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:52:36 +01:00
Niklas Eiling
d9e60e22b1 make it possible to specify a search path in PcieCard::make so we can use relative paths in config files 
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
 2023-03-21 11:15:25 +01:00