Niklas Eiling
8b95182b08
automatically configure and test Dino based on hwdef json
...
this currently requires manually adding the mapping of Dinos to i2c
buses in the fpga json.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-01-09 17:14:05 +01:00
Niklas Eiling
64d5a6ba42
fpgas.json: switch to new json per default and fix the same
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use fpga definition that includes dino and i2c controller to use the
latest bitstream (vc707-xbar-pcie-dino).
Fix the json for that bitstream to also include the interrupt
controller.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-01-09 17:14:05 +01:00
Niklas Eiling
4f4312127d
add json for vc707-xbar-pcie-dino
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2023-12-13 15:11:26 +01:00
Niklas Eiling
654ee84e9e
make FPGA device interface agnostic
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remove explicit mentioning of PCIe in the use of Device as a preparation
for integrating platform devices. auto formatted some files.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2023-12-12 14:08:34 +01:00
Niklas Eiling
d273162f71
fix PCIeCardFactory looking for IP config file at the wrong location
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2023-03-21 11:29:32 +01:00
Niklas Eiling
03f8d0782e
Revert "core: move configuration of polling mode to parse()"
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The changes lead to crashing because intc will not be configured
properly. Also revert removing configDone in ips/dma
This reverts commit 3b8949afe9
2022-12-05 10:36:45 +01:00
3b8949afe9
core: move configuration of polling mode to parse()
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:32 +01:00
14c7e57a8a
fix parsing of IP parameters
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2022-12-05 09:35:32 +01:00
Niklas Eiling
bac0b7309a
add card config option "polling" to configure polling mode in IP cores; add json parsing of hwdef to dma IP core to replace hardcoded DMA settings.
2022-11-11 04:53:58 -05:00
5060f07067
move VILLASnode configs to VILLASnode repo
2022-11-11 03:16:04 -05:00
7be3b049c7
update IPs config for new bitstream using MSI IRQs
2022-10-28 08:18:47 -04:00
26231dc78c
add example config for VILLASnode integration
2022-10-27 06:02:20 -04:00
80abbb866b
add latest vc707 config
2022-10-27 06:01:42 -04:00
9ef01d068e
update year in copyright notices
2022-08-30 12:22:40 -04:00
28262ef79b
remove old configs
2022-08-30 12:21:45 -04:00
53c4c4bf77
remove obsolete htdocs setting
2022-03-04 03:30:42 -05:00
Hatim Kanchwala
89f75c9a57
Remove old JSON config files
2020-07-04 15:11:00 +02:00
Hatim Kanchwala
73e85f2e5a
Add intial header file for Aurora
2020-05-26 14:46:35 +02:00
dd1a17c4a5
update bitstream configs
2019-08-15 13:57:29 +02:00
2112038d70
Merge branch 'feature/hls-rtds2gpu' into develop
2018-08-21 13:51:32 +02:00
7fd6599ea6
update copyright years
2018-06-25 15:33:14 +02:00
Daniel Krebs
194c4e3eef
etc: update fpga.json with changes related to stream routing
2018-06-04 17:36:36 +02:00
Daniel Krebs
5c67dc3727
rtds2gpu: update vlnv to match v1.1 and adapt config to new bitstream
2018-06-04 17:36:15 +02:00
Daniel Krebs
bf286568dd
rtds2gpu IP works
2018-06-04 17:36:15 +02:00
Daniel Krebs
68e5481d97
config: new config for changed bitstream
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AXI-BAR0 on PCIe bridge now allows access to whole PCI address space.
2018-05-15 18:04:24 +02:00
Daniel Krebs
73c6ae1f71
hwdef-parse: follow OR-gate merging DMA interrupts
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Also update JSON config with the new output.
2018-02-14 14:34:03 +01:00
Daniel Krebs
95adaad32f
etc/json: update config file with current output of hwdef-parse
2018-02-14 07:26:39 +01:00
daniel-k
92aea92f19
etc: update fpga.json with output of hwdef-parse
2018-01-23 14:43:53 +01:00
daniel-k
f94476b716
ip/node: rename OtherIpNode to StreamPort and other to to
2018-01-10 11:02:08 +01:00
daniel-k
4d3e4dd931
ips: make irqs a list
2018-01-10 11:02:08 +01:00
daniel-k
12024d53e5
lib/ip-node: add IpNode class, IpCore which has streaming ports
2018-01-10 11:02:08 +01:00
daniel-k
a5b5e317d4
wip implementing dependency parsing and proper memeory handling
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works and compiles so for. next is to implement different IP interfaces
(Model, Interface, DataMover, Infrastructure, ...)
2018-01-10 11:02:08 +01:00
daniel-k
eeafb2bcc6
etc/fpga: card is in slot 03:00.0 currently
2017-11-28 12:06:26 +01:00
daniel-k
c67c8aac5b
tests: add fpga.json and correctly parse it for unit tests
2017-11-22 19:46:07 +01:00
c3164e93ef
imported source code from VILLASfpga repo and made it compile
2017-11-21 21:31:08 +01:00
