Niklas Eiling
1710bc48d4
fpga: make compatible to new bitstream iteration
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-11-15 10:36:58 +00:00
Niklas Eiling
68ecc1a85a
fpga: remove duplicate ignore_ip_names
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-11-15 10:36:58 +00:00
Pascal Bauer
feccfea9f1
remove unused members
2024-11-15 10:36:58 +00:00
Pascal Bauer
9f12b9b050
update description
2024-11-15 10:36:57 +00:00
Pascal Bauer
4fca301046
remove dead code
2024-11-15 10:36:57 +00:00
Pascal Bauer
e79ee30587
remove dead code
2024-11-15 10:36:57 +00:00
Pascal Bauer
3654076c0c
add ignored ips
2024-11-15 10:36:57 +00:00
Pascal Bauer
5d883bda74
platform intc
2024-11-15 10:36:57 +00:00
Pascal Bauer
7cc05f9e17
platform irq draft
2024-11-15 10:36:57 +00:00
Pascal Bauer
768284549b
add platform card
2024-11-15 10:36:35 +00:00
Pascal Bauer
096202673d
add connect to vfio
2024-11-15 10:36:35 +00:00
Pascal Bauer
dde382c382
add json parser
2024-11-15 10:36:35 +00:00
Pascal Bauer
41a1edf07a
add card parser
2024-11-15 10:36:35 +00:00
Pascal Bauer
0ffda1b994
add zynq ip
2024-11-15 10:36:35 +00:00
Niklas Eiling
9afee0b044
fpga: remove exceptions from AxisCache
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-11-13 11:00:22 +01:00
Niklas Eiling
97090e9de5
fpga: Add new Dino configuration register that allows triggering the DAC before the time step to dino.cpp
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-11-13 11:00:22 +01:00
Niklas Eiling
56969defbf
fpga: Add driver for new register interface of axis cache IP
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-11-13 11:00:22 +01:00
e5ab276566
fix: Formatting
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-11-04 10:30:14 +01:00
Pascal Bauer
5e23100df9
feat: add parsing for ip-ignorelist
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-10-31 15:21:30 +01:00
Pascal Bauer
ee83bb197b
feat: ips can be ignored to be initialized in corefactory
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-10-31 15:21:30 +01:00
Steffen Vogel
1520743f73
fix: Formatting with clang-format
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-10-31 12:18:20 +01:00
Steffen Vogel
28d354cb84
Fix formatting with clang-format
...
Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-10-15 19:31:49 +02:00
Pascal Bauer
83e95f88a5
Refactor: change namespace pci to devices
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-08-30 12:23:02 +02:00
Pascal Bauer
975c02dc7d
Refactor: rename pci class to pci_device
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-08-30 12:23:02 +02:00
Pascal Bauer
91b541943e
Refactor: Move pci to devices/pci_device
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-08-30 12:23:02 +02:00
Niklas Eiling
f25e1dd689
log: fix undefined intitialization order of static objects. fixes #799 .
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-08-05 14:57:13 +02:00
Pascal Bauer
81f8981783
add member and getter for baseaddress
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-07-29 11:29:03 +02:00
Pascal Bauer
80fa0429dd
change name of "parseVLNV" to "parseIpIdentifier"
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
7d37c56947
move ip initialization into function
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
05f7a03909
move configure ips into function
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
cb53713953
move reordering of ips into function
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Pascal Bauer
823ba3281e
move VLNV parsing to function
...
Signed-off-by: Pascal Bauer <pascal.bauer@rwth-aachen.de>
2024-06-27 09:54:58 +02:00
Niklas Eiling
aeda901e47
fpga: use separate locks for write and read to allow them to be used concurrently
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-05 12:30:24 +02:00
Niklas Eiling
12af65b2b4
fpga: move register config for dino to DinoAdc
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-05-29 09:18:00 +02:00
Niklas Eiling
c151be5cca
fpga: fix includes and various comments
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
f1776f8be4
fpga: improve comments for fastRead and fastWrite
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
2cc8cad115
fpga: expose methods for finer control over DMA data path
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
248a4b3a0d
fpga: improve dma latency
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
Niklas Eiling
57d7396c09
fpga: optimize sg descriptor rings
...
we are now using only one memory block for both sg rings. This is
required so that the SG interface can benefit from a read cache
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-04-19 10:09:47 +02:00
a2d55a9b6e
Harmonize descriptions of plugins
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-04-10 09:06:15 +02:00
Niklas Eiling
ca03e1d406
fpga: enable using Xilinx xdma IP as DMA to AXI bridge as required for Ultrascale+ FPGAs
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-03-14 16:07:45 +01:00
3d73c759ea
Reformat all code with clang-format
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 19:34:27 +01:00
29cf5540a0
Fix some compiler warnings in fpga code
...
Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-02-29 19:33:40 +01:00
Niklas Eiling
542132de92
add API for createCards without std::filesystem
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 16:53:38 +01:00
Niklas Eiling
8a40b873be
register: fix wrong fomatter declaration
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 15:11:58 +01:00
Niklas Eiling
d24a323e5c
utils: remove cards from createCard
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 11:50:44 +01:00
Niklas Eiling
fb742dddd1
register: increase register num to 8
...
the VHDL changed so we need to change register here too
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 11:50:44 +01:00
Niklas Eiling
4b7ed781c0
card: add API to create a single card
...
this is a preparation for allowing defining the card in the node config
rather than separately.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-26 11:50:44 +01:00
Niklas Eiling
d54e4eb3f0
ips/register: add IP for the new register interface
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-14 14:20:33 +01:00
Niklas Eiling
c730412e98
ips/intc: move deinit to stop instead of destructor
...
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-02-14 14:20:33 +01:00
