18 commits

Author	SHA1	Message	Date
Steffen Vogel	c906116d86	update to latest VILLAScommon submodule	2020-06-11 14:20:33 +02:00
Steffen Vogel	7409d2024d	add more copyright / license headers	2018-06-25 17:03:09 +02:00
Steffen Vogel	7fd6599ea6	update copyright years	2018-06-25 15:33:14 +02:00
Daniel Krebs	e66350dbf6	tests: minor fixes in logging	2018-02-14 07:28:25 +01:00
Steffen Vogel	8206f867a5	logging: use similar log style in all modules	2018-01-31 20:24:11 +01:00
Steffen Vogel	51a3d0b8e9	tests: some cleanups	2018-01-31 20:22:15 +01:00
Steffen Vogel	b0f4577dd3	tests: automatically detect whether or not we can run tests in parallel	2018-01-31 15:12:19 +01:00
Steffen Vogel	0aed1a1b12	tests: moved initialization of FPGA stuff to fpga.cpp	2018-01-31 15:11:13 +01:00
Daniel Krebs	3de2170ad6	tests: move variables to global state and set criterion jobs to 1	2018-01-31 11:17:21 +01:00
Daniel Krebs	f6c02b8429	lib: add directed graph implementation incl. unittest	2018-01-30 15:13:23 +01:00
daniel-k	61de103c9e	tests/main: assert that there's an fpga	2018-01-16 15:08:56 +01:00
daniel-k	3cf50db98d	logging: use new spdlog library in favor of Logger	2018-01-10 15:49:53 +01:00
daniel-k	71a54eeab6	lib/ips: implement fifo driver and adapt test	2018-01-10 11:02:08 +01:00
daniel-k	018c89a2b0	tests/main: C++-ify	2018-01-10 11:02:08 +01:00
daniel-k	a5b5e317d4	wip implementing dependency parsing and proper memeory handling ... works and compiles so for. next is to implement different IP interfaces (Model, Interface, DataMover, Infrastructure, ...)	2018-01-10 11:02:08 +01:00
daniel-k	e590d1a350	add namespace villas::fpga and villas::fpga::ip and some renaming	2018-01-10 11:02:08 +01:00
daniel-k	b0e55e6fb2	current wip implementing card, many changes in ip too	2018-01-10 11:02:08 +01:00
daniel-k	d63c2b30bf	tests: compile main as C++	2018-01-10 11:02:08 +01:00

Renamed from fpga/tests/main.c (Browse further)