Niklas Eiling
bc2319771b
hook: initialize signals with an empty list
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This created issues when using hooks without a SuperNode. Some code assumes signals != nullptr.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
45307bcc16
node: avoid segfaults when signals are nullptr
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This can be an issue if we use a node without SuperNode.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
d473b36060
dp hook: use .c_str to convert from std::string
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
b5cd0e530c
fpga: do not return poll FDs if we are not using FDs
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
b4ef71aa74
fpga: fix wrong unpack string for config parsing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
f688640059
fpga: use separate locks for write and read to allow them to be used concurrently
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
6180e1019d
fpga: use snake case for low_latency_mode
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
8320e4f7c3
fpga: improve comments and removed dead code
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
4017441bf3
fpga: use constants to access registers
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
bf84044ca4
fpga: remove commas from conf
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
c4d2468268
fpga: remove output from performance critical code
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
851f66050c
fpga: convert SignalType to string before printing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
08a26bf324
DP hook: fix if that is never reached and check config in check()
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
1e0bfa9b73
fpga: make dino sampling rate configurable at top level and via json
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
bb57c75a4b
fpga: move register config for dino to DinoAdc
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
5e0f7e06c5
fpga: update libxil subreport so we support 64-bit addressing
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
Niklas Eiling
ddbe16c841
fpga: fix empty search path being an error
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:43 +02:00
c168838773
Fix missing idle_stop setting in integration tests
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
d6c04f4cb1
Revert default sample length to 64
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0049540e9d
test_rtt: Disable integration test in CI
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
4be302b480
test_rtt: Fix possible use of uninitialized variable
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
937242ca84
test_rtt: Add missing cooldown phase in runtime estimation
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
3c7fca7ce6
Increase default sample length
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0765e456fa
test_rtt: Fix logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6c6d37d00d
webrtc: Improve logging
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
7848dd7019
test_rtt: Fix compiler errors
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6114f6dcc2
webrtc: Show connection details
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
69b00f8915
test_rtt: Improve handling of defaults
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
b4b86aa220
test_rtt: Print estimated test durations
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0601ede07b
test_rtt: Rework calculation of test duration
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
19982bf49b
test_rtt: Improve statistics
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
f75bf8536c
webrtc: Enable ICE TCP
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
6efaa9e55b
test_rtt: Another round of new features
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
bae0a37526
format: Allow printing test meta data to result file
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
247f1ead42
csv, tsv: Fix printing of optional fields
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
f695225a3a
test_rtt: Fix wrong option identifier
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
7f857f392c
Fix formatting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
36220d3308
format-all: Exclude third-party or generated code
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
ffe804e177
iec61850_sv: Fix IEC 61850-9-2 Sampled Values node and unit test
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
550eb14758
super_node: Fix configuration of idle_stop setting
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
0ae86790b6
test_rtt: Fix test case numbering
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
d0b9bd5935
test_rtt: Stop test cases properly in order to close file handles
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:43 +02:00
59a76927fd
webrtc: Fix libdatachannel version detection
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Signed-off-by: Steffen Vogel <post@steffenvogel.de>
2024-06-18 12:39:42 +02:00
Steffen Vogel
d867880e2c
hypersim: Update UCM code for multiple signal values
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Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
2024-06-18 12:39:42 +02:00
Niklas Eiling
a6751c4c6e
fpga: improve comments in register.cpp
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
28c24ea22a
fpga: fix includes and various comments
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
0ae08e8434
fpga: improve comments for fastRead and fastWrite
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
98c1f36a02
fix formatting in fpga
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
87a1628c4a
fpga: add lowLatencyMode setting
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This setting improves latency by remove various checks.
Use with caution! Requires read cache in FPGA design!
The common use case in VILLASfpga is that we have exactly
one write for every read and the number of exchanged signals
do not change. If this is the case, we can reuse the buffer
descriptors during reads and write, thus avoidng freeing,
reallocating and setting them up.
We set up the descriptors in start, and in write or read,
we only reset the complete bit in the buffer descriptor and
write to the tdesc register to start the DMA transfer.
Improves read/write latency by approx. 40%.
Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
Niklas Eiling
d03b19613f
fpga: update ips json in fpga.conf
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Signed-off-by: Niklas Eiling <niklas.eiling@eonerc.rwth-aachen.de>
2024-06-18 12:39:42 +02:00
