Update copyright year in source files and examples.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
Update copyright year in source files and examples
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
This patch makes changes to fix warnings in the OpenAMP echo test app.
Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Acked by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch changes the mld file to enable the queue set option by
default.
Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Acked by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch corrects the hsize and stride alignment logic when DRE
is not enabled in the design.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
- Added dynamic scaler filter selection logic
- Added indirection layer for sub-core API's (picture settings,
PIP background color, debug information)
- Fixed VDMA alignment in 1/2/4 pixel configurations
- Added example directory. Included files to be uused with
vpss example design that will be released separately
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
There are 4 filter coefficient tables available. The table to be
loaded in IP register bank is determined by the scaling ratio
Scale Up: Always use 6tap
Scale Dn: Different table selected based on scaling ratio
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
There are 4 Filter coefficient tables available. The table to be
loaded in the IP is determined by the scaling ratio
Scale Up: Always use 6tap
Scale Dn: Different table selected based on scaling ration
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Updated API name to load external coefficients to align with
vprocss
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Updated API name to load external coefficients to align with
vprocss update.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Modify example to use the first available IPI device slot
for testing
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
When DRE is not enabled,adjust hsize and stride to memap data width on write channel(S2MM).
On read channel(mm2s), adjust hsize to stream data width and stride to memap data width.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the test_app tcl file so that polled,
interrupt tests are removed from the peripheral tests.
Since we dont know whether peripherals are connected to
SPIPS or not.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the test_app tcl file so that polled,
interrupt tests are removed from the peripheral tests.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch changes openamp rpc demo application linker script
to keep everything in DDR except vectors. It fixes the order
of text carve out memory.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-for-series: Anirudha Sarangi <anirudh@xilinx.com>
This patch changes linker script to keep everything into DDR
except vectors. It removes frequent call to enable interrupt
and removed disable interrupt in between. It also fixes the
order of text carve out entry.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-for-series: Anirudha Sarangi <anirudh@xilinx.com>
This patch updates the FreeRTOS Hello World Demo application to
make it more meaningful. Also it updates the tcl to make it work for
R5, A9 and MicroBlaze.
Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Acked by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
For CortexA9, the tcl was exporting a wrong hash define to clear
the interrupts. This patch fixes that issue.
Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Acked by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
The existing mld file has incorrect tick_setup category. The patch
fixes it. The patch also does some cleanup to remove unnecessary
comments.
Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>
Acked by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Currently R5 applications are handedoff immediately after they are loaded.
This feature is configurable in FSBL and now with this change, early handoff
is disabled by default. User can enable this feature again by defining
FSBL_EARLY_HANDOFF_EXCLUDE_VAL as 1.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch updates the Xil_SetTlbAttributes to mark the BD memory region
only uncaheable and updated the cache flush/invalidate api's for a53 case.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked by: Anirudha Sarangi <anirudh@xilinx.com>
-Updated driver structure, variable and API names to align with
defined coding guidelines
-Load scalers and chroma resampler coefficients only if the
instantiated configuration supports it
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Coefficient register base address offset changed in IP from
0x400 to 0x800 to accomodate all supported taps.
Split Phase and Coefficient programming logic in 2 independent
API's. For Bicubic and Bilinear scalers only Phase needs to
be programmed.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Coefficient register base address offset changed in IP from 0x400 to
0x800 to accomodate all supported taps.
Split Phase and Coefficient programming logic in 2 independent
API's. For Bicubic and Bilinear scalers only Phase needs to be
programmed.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Added enumeration for supported resampling algorithms.
Coefficients needs to be programmed only for FIR mode. Bounded
coefficient programmin API with required condition.
Updated debug API to report resampler type and associated
coefficients
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Added enumerations to describe supported resampling algorithms
Only FIR mode needs the programmable coeffiecients. Bounded the
coefficient programming API with the required condition.
Also updated debug API to report out the resampling type and
associated coefficients
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
IP bus name prefix changed from "AXILITES" to "CTRL" to align
with all other HLS IP's in video processing subsystem. Generated
driver updated.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
