Modify clock config function to move all ZynqMP GEM related code inside
XPAR_<psu ethernet ip> checks. This fixes the compilation errors for Zynq
that are caused by references to GEM2/3.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Write to CRL_APB registers for clock control and enable 1G speed.
Move clock configuration to a separate function.
Update payload to jumbo size.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Read the phy idetifier register to identify whether PHY is Marvell or TI.
Add support for TI PHY sequence by writing to PHY CNTRL register and
tuning using RGMIICTL/RGMIIDCTL registers.
Access to extended registers in TI pHY is through REGCR and ADDAR registers.
ADDAR should be used to write the offset of register to be written
and then the value to be written. REGCR should indicate when ADDAR contains
register offset and when it contains register data.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Enable jumbo option and use updated API's for zynqmp.
Increase array size to support jumbo frames - these can be decreased by user if
not required.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Added terminating descriptors for unused rx and tx queues to avoid
wrong interpretation of the data that resides in the memory location
ponited by the queue base registers.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Modified to use single BD for both rx and tx for avoiding the
multiple version checks and probabaly create another example
for multiple BD processing.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
