13 commits

Author	SHA1	Message	Date
Steffen Vogel	c906116d86	update to latest VILLAScommon submodule	2020-06-11 14:20:33 +02:00
Steffen Vogel	2112038d70	Merge branch 'feature/hls-rtds2gpu' into develop	2018-08-21 13:51:32 +02:00
Steffen Vogel	7409d2024d	add more copyright / license headers	2018-06-25 17:03:09 +02:00
Steffen Vogel	7fd6599ea6	update copyright years	2018-06-25 15:33:14 +02:00
Daniel Krebs	93fe1390d6	fix wrong usage of reinterpret_cast in ips and tests	2018-06-04 17:36:36 +02:00
Daniel Krebs	5097827757	fix include paths, use <villas/...> style	2018-06-04 13:24:57 +02:00
Daniel Krebs	acf273e406	tests: let them fail if no Fifo or Timer is found	2018-02-14 07:27:37 +01:00
Daniel Krebs	3de2170ad6	tests: move variables to global state and set criterion jobs to 1	2018-01-31 11:17:21 +01:00
daniel-k	e46720d23b	tests: improve logging	2018-01-23 14:43:30 +01:00
daniel-k	62e1a7d962	tests/fifo: fail if connecting loopback doesn't work	2018-01-23 14:43:06 +01:00
daniel-k	16455bdd13	tests/fifo: cleanup	2018-01-16 15:08:27 +01:00
daniel-k	3cf50db98d	logging: use new spdlog library in favor of Logger	2018-01-10 15:49:53 +01:00
daniel-k	71a54eeab6	lib/ips: implement fifo driver and adapt test	2018-01-10 11:02:08 +01:00

Renamed from fpga/tests/fifo.c (Browse further)