VTC in example design has switched to a slower 9MHz clock.This
essentially provides < 2fps frame rate. Vidout needs 3-4 frames
to acquire lock. After vpss configuration wait for 2 sec (mb_sleep)
before checking for vidout lock
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Vivado Example design tool flow change resulted in hdf file name
change of video processing subsystem example design. Update the
script to accept hdf file name from command line to avoid any
dependency on further name changes
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Updated the system.c to use canonical name for MIG to avoid
dependency on instance name
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
xsct scipt file added to automate the process of generating the
elf file(s) from the provided hdf file
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
- Added dynamic scaler filter selection logic
- Added indirection layer for sub-core API's (picture settings,
PIP background color, debug information)
- Fixed VDMA alignment in 1/2/4 pixel configurations
- Added example directory. Included files to be uused with
vpss example design that will be released separately
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
-Updated driver structure, variable and API names to align with
defined coding guidelines
-Load scalers and chroma resampler coefficients only if the
instantiated configuration supports it
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
-Bug fix for wrong pip background color when video format is
changed
-Input stream color depth and pixel/clock must be overwritten
by subsystem as these are not run time configurable
-Deinterlacer supports 480i/576i and 1080i. removed constraint
for 1080i support only
-Updated mdd file to reflect new drivers versions -
video_common_v2.0 and axivdma_v6.0, in dependency list
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
-Added logic to fix vdma ip alignement issues with different bit
width at axis and aximm interface at all supported pixel/clk
and color depth combinations
-Moved stream (input/output) validation logic scattered around
in different blocks to a central location
-Added API to report subsystem configuration status
-Code cleanup and changed relevant prints to dbg print
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
- Code cleanup to remove interrupt handler registration.
Subsystem does not have interrupts
- Updated sub-core init routines to load default filter
coefficients for scaler and chroma resamplers
- Added layer 2 registers for chroma resamplers
- Updated VDMA Read/Write interface to work with color depth
instead of Bytes/Pixel
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This patch supports HIP based video processing subsystem.
Added makefile and tcl to build the subsystem tree and updated
the driver to construct sub-core baseaddress
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
Underlying subcores now use model parameters to get the static
configuration. Update the subsystem drivers to use this
information. Also user defined scaler cofficient table is moved
to application code
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Video processing subsystem driver is added to the repo. This
driver currently is associated with a non-HIP version of the
IP. No makefile available. Hard-coded g.c file used, but not
included.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
