-Added structure PmSuspendRequest for tracking suspend request
related informations: which master is allowed to request whose
suspend, has the request been made, etc.
-Added functions in pm_master for handling requests
-Added calls in pm_proc for triggering acknowledge once primary
processor goes to sleep
-Added sending acknowledge if target master aborts suspend
-Timeouts to be implemented
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Changed code in PmUpdateSlave to first determine the state to be
entered
-Added function for finding the state with required capabilities
-Removed function which was finding and changing state of a slave
(not used anymore)
-Major reason for changing this code is the bug: in USB case,
when USB is already in right state and upon the set requirement
request which should be resolved to the same state (nothing to
configure, state is already configured as requested) PM
acknowledged an error, although there was no error
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
-Using int type for returns
-Error statuses are common Xilinx XST_* codes
-Additional power management status errors are defined in pm_defs.h
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Added reset assert for RPU0..1 processor's sleep functions.
Reset assert is done by directly writing into crl_apb registers,
becase pmu-rom does not expose function for only asserting reset.
Reset assert is a must in order to stop processor from executing
instructions once it's sleep handler gets executed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
-Added default requirements field in PmRequirements structure
-Added notification of master when primary processor switches from
forced powerdown to active state. Master has to make sure that all
default requirements gets set before primary processor enters active
state.
-In PmMasterNotify, changed behavior when wake event is received:
if primary processor is in sleep state, everything works as before,
if primary processor is in forced powerdown, default requirements
are requested and configured
-In PmRequirementReleaseAll added a check is master using slave and
if yes, usage flag and requirements are cleared
-Added PmRequirementRequestDefault function called before primary
processor switches from forced powerdown to active. Function
automatically requests all default requirements which are later
configured by PmRequirementUpdateScheduled
-In PmRequirementUpdateScheduled when swapping requirements added
a check whether master has default requirements. If yes, default
reqs are saved as next reqs instead of current. Default requirements
have priority over current requirement. Example: RPU0 keeps boot code
in one TCM bank and when booted, during the runtime, it keeps that
bank in retention. For this bank RPU0 should have default requirements
= on state, and when it boots up it can request retention. If default
requirements wouldn't exist, it would have to request for boot bank to
switch from retention to on before calling self suspend, just to get
on state in scheduled reqs
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Before, there was a check at the very beginning to see if current state
is having exact required capabilities. However, state should be checked
for having all required capabilities and not for having exact required
caps. Also, even when state have all required capabilities, there could
be state with lower power that still has all required capabilities.
Code is changed to implement above claims.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Removed action arrays and instId pointers used in PmSlaveFsm
-Removed unused macros and typedefs
-Removed redundant functions for Sram retention entry/exit
-Added enterState function in PmSlaveFsm. Slave state is entered
based on arguments (slave pointer and next state).
-Added xpbr function pointers in PmSlave derived objects (usb and sram)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
We should only enable the scheduled wake-up sources in the GIC Proxy
if the processor is sleeping.
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
A print format string had a typo in the conversion specifier.
Fixes: ae1b22f628eeae491136205dd99cac745bad5b54 "Scheduler: Add Scheduler files"
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Reserve the area in RAM that the ROM expects the extension hook table to
be in. Also provide a definition for the table in a header so FW can insert
entries easily, if needed.
Cc: Kristopher Bechamp <kristop@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
During programming the bit files as per flow
in case of errors need to do a full reset of mcap
config space. This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch modifies the Access Device Configuration Space
option to -a instead of -c.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch updaets README in the
driver for the updated changes.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch fixes the issues with the program files(.rbt,.bit)
handling.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch adds support for configuring
a partial clear file followed by a partial bit file.
(Ex: ./mcap -x 0x8038 -C partialclear.bit -p partial.bit)
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch adds support for programming the partial
Reconfiguration clear file.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch fixes the issue
Done pin doesn't go high after programming
the 2nd stage bit stream.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
when -d option is used to dump all the registers,
It should ignore the Data register if it's empty or
Not set and should not return a failure in reading those registers.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch adds the "Type" option of (b or h or w)
for the -c option when the help menu is printed.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
The MCAP interface enables an embedded microprocessor, such as MicroBlaze,
to read and write the FPGA configuration memory.
This library allows user to access the MCAP i/f.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
Added license.txt file - information about various licenses
and copyrights.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
PMU FW if present, is now handed off immediately after its load and validation.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Support added to handoff to R5 applications after thery are loaded.
This feature can be turned ON by using conditional switch.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch modifies the file size as 8KB to test on emulation
platform. Since 8MB in emulation platform taking long time,
reduced file size to 8KB.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch modifies the source code according to
MISRAC-2012.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modified cortexr5/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS correctly.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS to fix a bug introduced during new version creation
of BSP
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies xil_settlbattributes API to work with
addresses > 4GB by modifying the address masking value
appropriate for higher addresses lies beyond 4GB
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add a separate platform file for Zynq Ultrascale MPSoC using the
respective timer and driver functions. The platform selection is
based on the processor recognized in the tcl file.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add support for recognizing processor A53 or R5 to work for
Zynq Ultrascale MPSoC
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add support to be used with newer version of GEM in Zynq Ultrascale MPSoC.
Use TX Q1 and RX Q0; segregate Zynq specific TLB attributes and SLCR settings.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add support for lwip library to be picked for A53 & R5 and to use
necessary GIC. Comment informational prints.
This is to add support for Zynq Ultrascale MPSoC.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Modify makefile to check for IAR compiler to use --create and
remove individual checks for all other compilers.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the XUartLite_ReceiveBuffer function to
update the received data in critical region. Earlier the data
updation is outside the critical region.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch updates the iomodule_define_vector_table proc by
removing old hsi commands like xget_handle and also updates
the generate proc to get iomodule canonical definitions in
xparameters.h
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch renames DisplayPort TX Subsystem sub-core files name
with prefix xdptxss_, functions with prefix XDpTxSs_ and macors
with prefix XDPTXSS_.
Signed-off-by: Shadul Shaikh <shaduls@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This patch supports HIP based video processing subsystem.
Added makefile and tcl to build the subsystem tree and updated
the driver to construct sub-core baseaddress
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This patch supports HIP based video processing subsystem by reorganizing
the HLS generated code to align with xilinx driver guidelines.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This patch supports HIP based video processing subsystem by reorganizing
the HLS generated code to align with xilinx driver guidelines.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This patch supports HIP based video processing subsystem by reorganizing
the HLS generated code to align with xilinx driver guidelines.
Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
