Move the tracking of suspend requests into the corresponding master
structures.
This patch limits the number of possible requestors to 1.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added structure PmSuspendRequest for tracking suspend request
related informations: which master is allowed to request whose
suspend, has the request been made, etc.
-Added functions in pm_master for handling requests
-Added calls in pm_proc for triggering acknowledge once primary
processor goes to sleep
-Added sending acknowledge if target master aborts suspend
-Timeouts to be implemented
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Changed code in PmUpdateSlave to first determine the state to be
entered
-Added function for finding the state with required capabilities
-Removed function which was finding and changing state of a slave
(not used anymore)
-Major reason for changing this code is the bug: in USB case,
when USB is already in right state and upon the set requirement
request which should be resolved to the same state (nothing to
configure, state is already configured as requested) PM
acknowledged an error, although there was no error
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
-Using int type for returns
-Error statuses are common Xilinx XST_* codes
-Additional power management status errors are defined in pm_defs.h
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Added reset assert for RPU0..1 processor's sleep functions.
Reset assert is done by directly writing into crl_apb registers,
becase pmu-rom does not expose function for only asserting reset.
Reset assert is a must in order to stop processor from executing
instructions once it's sleep handler gets executed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
-Added default requirements field in PmRequirements structure
-Added notification of master when primary processor switches from
forced powerdown to active state. Master has to make sure that all
default requirements gets set before primary processor enters active
state.
-In PmMasterNotify, changed behavior when wake event is received:
if primary processor is in sleep state, everything works as before,
if primary processor is in forced powerdown, default requirements
are requested and configured
-In PmRequirementReleaseAll added a check is master using slave and
if yes, usage flag and requirements are cleared
-Added PmRequirementRequestDefault function called before primary
processor switches from forced powerdown to active. Function
automatically requests all default requirements which are later
configured by PmRequirementUpdateScheduled
-In PmRequirementUpdateScheduled when swapping requirements added
a check whether master has default requirements. If yes, default
reqs are saved as next reqs instead of current. Default requirements
have priority over current requirement. Example: RPU0 keeps boot code
in one TCM bank and when booted, during the runtime, it keeps that
bank in retention. For this bank RPU0 should have default requirements
= on state, and when it boots up it can request retention. If default
requirements wouldn't exist, it would have to request for boot bank to
switch from retention to on before calling self suspend, just to get
on state in scheduled reqs
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Before, there was a check at the very beginning to see if current state
is having exact required capabilities. However, state should be checked
for having all required capabilities and not for having exact required
caps. Also, even when state have all required capabilities, there could
be state with lower power that still has all required capabilities.
Code is changed to implement above claims.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Removed action arrays and instId pointers used in PmSlaveFsm
-Removed unused macros and typedefs
-Removed redundant functions for Sram retention entry/exit
-Added enterState function in PmSlaveFsm. Slave state is entered
based on arguments (slave pointer and next state).
-Added xpbr function pointers in PmSlave derived objects (usb and sram)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
We should only enable the scheduled wake-up sources in the GIC Proxy
if the processor is sleeping.
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
A print format string had a typo in the conversion specifier.
Fixes: ae1b22f628eeae491136205dd99cac745bad5b54 "Scheduler: Add Scheduler files"
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Reserve the area in RAM that the ROM expects the extension hook table to
be in. Also provide a definition for the table in a header so FW can insert
entries easily, if needed.
Cc: Kristopher Bechamp <kristop@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
PMU FW if present, is now handed off immediately after its load and validation.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Support added to handoff to R5 applications after thery are loaded.
This feature can be turned ON by using conditional switch.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Add a separate platform file for Zynq Ultrascale MPSoC using the
respective timer and driver functions. The platform selection is
based on the processor recognized in the tcl file.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add support for recognizing processor A53 or R5 to work for
Zynq Ultrascale MPSoC
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Changed the location of temporary ddr address definition.
This address is for storing PL bitstream temporarily.
User can change this address till support is provided in bootgen
(for load address configuration for PL).
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Added checks to power up power islands, if required, before first access.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This fix stores FSBL's ATF Handoff parameters at fixed address towards
end of OCM so that ATF can avoid conflict with its sections.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
For SD and eMMC, BIN filenames now follow convention BOOTXXXX.BIN.
FSBL now updated as per this change.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Xil_DCacheDisable() function internally has call to Xil_DCacheFlush().
Hence removing redundant calls to Xil_DCacheFlush from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Exception handlers are now registered unconditionally for both A53 and R5
Removed enabling of IRQ from FSBL(to be enabled in user application)
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
While creating new FSBL+BSP project, made xilsecure library
to be selected by default. This avoids compilation errors
when FSBL project is created.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
When authentication of partitions is not enabled, decryption is failing.
This patch fixes this issue.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch does the changes in FSBL to match the signature changes of
few functions in xilsecure library.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
swbeta2 commit 1b173007d1cc009bffeb2969a5a5bacc533647db
IPI0 is used by PMUFW for PM requests and the mask is used for determining
the Master. There are chances of IPIs being triggered before FW Init but
un-handled or even bits that are not cleared by ROM, causing a corruption
of the ISR mask. So PMUFW should cleanup these bits during startup
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
swbeta2 commit 572db0eb0f48b4f7f5684abea721c6fac92ccdee
When powering up the RPU island the individual RPU core resets as well
as the reset for the whole island are asserted. To ensure proper resume,
the island reset needs to be released when the island is powered up.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
swbeta2 commit ae6d9a98edb99ce4c51c85bce4872a9f11c7eb74
PMU Firmware is being updated to the latest code base available
in the pmufw git repo. Major changes are:
-Error Management is enabled by default
-PM Module bug fixes
-Code formatting changes
-PMU ROM handlers use ROM Table instead of
individual handler addresses
-Bug fixes in scheduler
-FW_IS_PRESENT bit is set if PM is enabled
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Support for decryption of images added.
Authentication and decryption now use secure library APIs.
csu dma driver APIs are used now.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Corresponding fields in the devcfg.STATUS register are written to,
for clearing DMA done count.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
