Added source files, integration files, self test example,
mdd and tcl files to cfa driver.
Signed-off-by: Shravan Kumar A <skumara@xilinx.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Added source files, integration files, self test example,
mdd and tcl files to enhance driver.
Signed-off-by: Shravan Kumar A <skumara@xilinx.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
When enabling slave monitor, clear FIFO, enable read mode and clear
the transfer size register.
NACK interrupt should not be enabled as this will lead to the sw
being interrupted everytime a retry fails.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
This patch uses the data typess from stdint.h (in the toolchain
instead of type defining standard data types. This addition
makes the file xil_types.h independent of 32/64-bit platform.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch adds notes for the Xil_ExceptionInit function for
modification of exception handler initilization.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch fixes issue of multiple definition of function in
toolchain and BSP for some special cases.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch fixes the issue of improper linking of translation_table.s
by changing the cortexa9/armcc/Makefile
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch enables asynchronous abort exception in boot.s and
adds default exception handler for data abort and prefetch abort
for debug purpose.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch fixes issue of IAR compilation error of standalone BSP for cortexa9
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch fixes the issues in the xilkernel tcl file
Using MB & Xilkernal with config_bufmalloc with config_msgq fails with unclear error
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch fixes the issue of wrong interrupt being
get exported to the xemacltie_topolgy_g.c file
in the lwip.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
There is an issue with HSM TCL in LWIP, which fails to parse the
BSP name properly and hence Xilkernel/FreeRTOS BSP doesn't compile
if LwIP library is added with SOCKET_API mode enabled. This patch
fixes this issue by correcting the LWIP tcl.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch removes this line and doing so it allows to output the
xdbg_printf() debug logs when -DDEBUG flag is enabled for BSP.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch adds support for iar compiler into standalone BSP for cortexa9
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Some of the LWIP options like memp_num_tcpip_msg, memp_num_api_msg
are configurable from LWIP settings, but they are not actually
set when compiling the LWIP library. This patch modifies the LWIP
tcl to update them.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Currently, the AXI Ethernet adapter is configured to support only
Marvel PHYs which exist on all Xilinx boards. This patch allows
to get the auto-negotiation speed of any PHY using IEEE specification.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Change CR_RESET_STATE defintion to include required bits to be set and
reset. When writing to the configuration register, read the register and
OR the required value to leave the reserved bits untouched.
Changes done in XQspiPs_Reset function and HW reset function.
The default value written was expanded to include setting hold bit and
using manual chip select (This is recommended and already explicitly
followed in all the examples).
Removed check for register values in selftest because a reset is done
in just the previous step where default values are already written.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
