Added BBRAM PS programming APIs for Zynq MP platform
In BBRAM there is no provision for saperate CRC check
CRC check can be performed only while programming AES key
So user no need to calculate CRC of key if they provide key
for programming CRC check will also be performed internally.
User can also make BBRAM key to Zero at any time.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
For ZynqMp platform's Efuse PS interface functions are added.
In efuse PS we can programm AES, User keys and PPK0, PPK1 hashs
SPK Id, JTAG user code and including some control bits.
If Tbits are not programmed some programming features can't be
programme, user no need to call any API to program this Tbits
they are programmed internally when you tried to program any
of the programming bits if Tbits are not programmed on efuse.
PPK hash accepts input in the form bootgen's hash output
user no need to change HASH.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modified CRC calculation API to calculate CRC of
ZynqMP efuse PS's AES CRC.
Added Ceil function to calculate ceil.
Added write and read registers APIs.
Modified Xilskey_CrcCalculation API to
XilSKey_CrcCalculation
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
According to IEEE 1149.1 programming will start after
TCK toggle at higher edge of clock and will be ended at
RTI state change and followed TCK toggle.
So JtagWrite API is modified accordingly.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
DFT control bits of efusePS for Zynq Platform is
added.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modified if condition at programming the
secure row of ultrascale's efuse.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Acked-by: Harini Katakam <harinik@xilinx.com>
As GpioPs and Timers are different for Ultrascale
all the calls related to Gpio and timers are saperated
by ifdefinitions.
Added new jtag function to access efuse of Ultrascale.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
To add ultrascale's efuse functionality added GPIO pins
and GPIO channels to access master JTAG, Fpga_Flag to tell
the FPGA series, AES CRC check flag and AES CRC value, RSA key
hash to program and RSA key hash read back and control and
secure parameters in PL instance and modified IR length
macro ZYNQ_TAP_IR_LENGTH to TAP_IR_LENGTH as IR length is same for both
Zynq and Ultrasale.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Removed redundant code by adding common API for clock
calculations.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch initialises RSAKeyReadback value with zero's since
if RSA key is read with XSK_EFUSEPS_ENABLE_RSA_KEY_HASH as FALSE
then it will return zero.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies files to fix warnings that got
generated when -Wextra flag was used.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch deprecates the old v2.0 version and created
new v2.1 version for xilskey library.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
