XpbrPwrUpFpdHandler used to not always return XST_SUCCESS, this
problem no longer exists hence the workaround can be dropped.
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added PLL nodes (PLLs are PM slaves)
-Implemented PLL's FSM in pm_pll.h/c
-Added PmRequirement structures for APU and RPU_0, both can request
any PLL for usage
-Implemented saving of FPD PLLs' context and powering down FPD PLLs
before FPD gets powered down (this is PLL suspend)
-Implemented restoring of PLL states when PLL is needed for usage
if FPD has been powered down (this is PLL resume)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added array of CRF_APB module's register address/value pairs used
for saving/restoring CRF_APB register contents (excluding PLL
registers - PLLs have their own logic for save/restore)
-Added saving context of CRF_APB registers before FPD is powered
down and restoring saved context after FPD is powered up
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added PM_CAP_POWER as generic capability (defined in pm_defs).
-Slaves' FSMs should define PM_CAP_POWER capability in states which
require power parent to be ON before the state is entered. This
capability has no effect if slave node does not have power parent
-Powering up parent of a slave is done automatically by the
framework before the FSM of a slave is triggered to change the
state (slave's FSM should assume all prerequisites regarding power
are configured before FSM is triggered)
-Added PM_CAP_POWER capability in ON state of standard fsm (used for
SATA)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-There was a bug in pmu-fw/pm binding through IPIs, because of
which in case of multiple IPI interrupts generated simultaneously
only first interrupt was handled, other interrupts were lost
-The bug existed because PM handles one request in each
XPfw_PmIpiHandler invocation, and pmu-fw clears all bitfields
in ISR register after PM handles request. Therefore, if multiple
bits were set in ISR register (simultaneous IPI interrupts), only
first one was handled and other bits were just cleared
-XPfw_PmIpiHandler now returns status and through an argument
pointer an IPI mask of master whose request has been handled
-In xpfw_user_startup.c/PmIpiHandler, return of XPfw_PmIpiHandler
is checked. If PM successfully handled IPI, only the bitfield of
master whose request is handled is set (only that IPI interrupt
is cleared). If something went wrong in PmIpiHandler/IPI0 case,
we clear all bits set in ISR register, to avoid system hanging on
this interrupt handler
-In pm_master, a check whether the master owns given mask was
performed by using '==' instead '&'. Therefore, when 2 masters
generated interrupt at the same time, PM function that checks
whether the IPI is PM related returned that the ISR value does
not match any master. This bug is fixed
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Replaced PM defined macro definitions with macros defined in
lpd_slcr.h
-Other macros that are defined in pm_slave.h do not exist as is,
therefore are still used
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added macros in pm_defs.h for system shutdown argument 'restart'
-Exposed array of all masters needed to initiate their suspend upon
receiving of system shutdown call
-Added checking for restart argument of system shutdown call in pm_api.c
-Implemented PmSystemShutdown for argument restart=0 (shutdown)
-Further improvement in PmSystemShutdown depend on timeout implementation
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Every master has unique bitfield in all IPI registers
-PMU power management accesses status, trigger and enable registers
for a master using the unique master's ipiMask now
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Move the tracking of suspend requests into the corresponding master
structures.
This patch limits the number of possible requestors to 1.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Added structure PmSuspendRequest for tracking suspend request
related informations: which master is allowed to request whose
suspend, has the request been made, etc.
-Added functions in pm_master for handling requests
-Added calls in pm_proc for triggering acknowledge once primary
processor goes to sleep
-Added sending acknowledge if target master aborts suspend
-Timeouts to be implemented
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Changed code in PmUpdateSlave to first determine the state to be
entered
-Added function for finding the state with required capabilities
-Removed function which was finding and changing state of a slave
(not used anymore)
-Major reason for changing this code is the bug: in USB case,
when USB is already in right state and upon the set requirement
request which should be resolved to the same state (nothing to
configure, state is already configured as requested) PM
acknowledged an error, although there was no error
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
-Using int type for returns
-Error statuses are common Xilinx XST_* codes
-Additional power management status errors are defined in pm_defs.h
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Added reset assert for RPU0..1 processor's sleep functions.
Reset assert is done by directly writing into crl_apb registers,
becase pmu-rom does not expose function for only asserting reset.
Reset assert is a must in order to stop processor from executing
instructions once it's sleep handler gets executed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
-Added default requirements field in PmRequirements structure
-Added notification of master when primary processor switches from
forced powerdown to active state. Master has to make sure that all
default requirements gets set before primary processor enters active
state.
-In PmMasterNotify, changed behavior when wake event is received:
if primary processor is in sleep state, everything works as before,
if primary processor is in forced powerdown, default requirements
are requested and configured
-In PmRequirementReleaseAll added a check is master using slave and
if yes, usage flag and requirements are cleared
-Added PmRequirementRequestDefault function called before primary
processor switches from forced powerdown to active. Function
automatically requests all default requirements which are later
configured by PmRequirementUpdateScheduled
-In PmRequirementUpdateScheduled when swapping requirements added
a check whether master has default requirements. If yes, default
reqs are saved as next reqs instead of current. Default requirements
have priority over current requirement. Example: RPU0 keeps boot code
in one TCM bank and when booted, during the runtime, it keeps that
bank in retention. For this bank RPU0 should have default requirements
= on state, and when it boots up it can request retention. If default
requirements wouldn't exist, it would have to request for boot bank to
switch from retention to on before calling self suspend, just to get
on state in scheduled reqs
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Before, there was a check at the very beginning to see if current state
is having exact required capabilities. However, state should be checked
for having all required capabilities and not for having exact required
caps. Also, even when state have all required capabilities, there could
be state with lower power that still has all required capabilities.
Code is changed to implement above claims.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
-Removed action arrays and instId pointers used in PmSlaveFsm
-Removed unused macros and typedefs
-Removed redundant functions for Sram retention entry/exit
-Added enterState function in PmSlaveFsm. Slave state is entered
based on arguments (slave pointer and next state).
-Added xpbr function pointers in PmSlave derived objects (usb and sram)
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
We should only enable the scheduled wake-up sources in the GIC Proxy
if the processor is sleeping.
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
A print format string had a typo in the conversion specifier.
Fixes: ae1b22f628eeae491136205dd99cac745bad5b54 "Scheduler: Add Scheduler files"
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Reserve the area in RAM that the ROM expects the extension hook table to
be in. Also provide a definition for the table in a header so FW can insert
entries easily, if needed.
Cc: Kristopher Bechamp <kristop@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Jyotheeswar Reddy <jyothee@xilinx.com>
During programming the bit files as per flow
in case of errors need to do a full reset of mcap
config space. This patch fixes this issue.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch modifies the Access Device Configuration Space
option to -a instead of -c.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch updaets README in the
driver for the updated changes.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch fixes the issues with the program files(.rbt,.bit)
handling.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch adds support for configuring
a partial clear file followed by a partial bit file.
(Ex: ./mcap -x 0x8038 -C partialclear.bit -p partial.bit)
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch adds support for programming the partial
Reconfiguration clear file.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch fixes the issue
Done pin doesn't go high after programming
the 2nd stage bit stream.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
when -d option is used to dump all the registers,
It should ignore the Data register if it's empty or
Not set and should not return a failure in reading those registers.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
This patch adds the "Type" option of (b or h or w)
for the -c option when the help menu is printed.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
The MCAP interface enables an embedded microprocessor, such as MicroBlaze,
to read and write the FPGA configuration memory.
This library allows user to access the MCAP i/f.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
Added license.txt file - information about various licenses
and copyrights.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Srikanth Vemula <svemula@xilinx.com>
PMU FW if present, is now handed off immediately after its load and validation.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Support added to handoff to R5 applications after thery are loaded.
This feature can be turned ON by using conditional switch.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch modifies the file size as 8KB to test on emulation
platform. Since 8MB in emulation platform taking long time,
reduced file size to 8KB.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch modifies the source code according to
MISRAC-2012.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modified cortexr5/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS correctly.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS to fix a bug introduced during new version creation
of BSP
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies xil_settlbattributes API to work with
addresses > 4GB by modifying the address masking value
appropriate for higher addresses lies beyond 4GB
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add a separate platform file for Zynq Ultrascale MPSoC using the
respective timer and driver functions. The platform selection is
based on the processor recognized in the tcl file.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add support for recognizing processor A53 or R5 to work for
Zynq Ultrascale MPSoC
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Add support to be used with newer version of GEM in Zynq Ultrascale MPSoC.
Use TX Q1 and RX Q0; segregate Zynq specific TLB attributes and SLCR settings.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
