Set speed of 1G for silicon only and run at 100Mbps on emulation platforms.
CRL_APB register configuration to 1000Mbps is also only required for silicon.
Minor comment corrections done.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Different GEM instances are present on evaluation and emulation platforms
of Zynq Ultrascale+ MPSoC.
To allow for automatic testing, select XPS_GEMx_INTR_ID based on the
PSU_<> present. Left initial definition intact for Zynq.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Modify clock config function to move all ZynqMP GEM related code inside
XPAR_<psu ethernet ip> checks. This fixes the compilation errors for Zynq
that are caused by references to GEM2/3.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Write to CRL_APB registers for clock control and enable 1G speed.
Move clock configuration to a separate function.
Update payload to jumbo size.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Enable jumbo option and use updated API's for zynqmp.
Increase array size to support jumbo frames - these can be decreased by user if
not required.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Added terminating descriptors for unused rx and tx queues to avoid
wrong interpretation of the data that resides in the memory location
ponited by the queue base registers.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Modified to use single BD for both rx and tx for avoiding the
multiple version checks and probabaly create another example
for multiple BD processing.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
