63a1eb2f7f
remove some obsolete C code files
2018-06-25 17:22:31 +02:00
7409d2024d
add more copyright / license headers
2018-06-25 17:03:09 +02:00
7fd6599ea6
update copyright years
2018-06-25 15:33:14 +02:00
Daniel Krebs
d853d5e0d3
wip GPU RTT
2018-06-06 09:55:14 +02:00
Daniel Krebs
f7781d47af
tests/rtds2gpu: cleanup
2018-06-05 14:56:43 +02:00
Daniel Krebs
2a56f5ff13
tests/rtds2gpu: fix doorbell offset
2018-06-05 14:48:35 +02:00
Daniel Krebs
49f0c2e0c4
unit test RTT via CPU to/from RTDS works!
2018-06-04 19:06:36 +02:00
Daniel Krebs
92bfe849b4
ips/rtds2gpu: use new connect interface
2018-06-04 17:36:36 +02:00
Daniel Krebs
f413712b86
gpu2rtds: unit test working
2018-06-04 17:36:36 +02:00
Daniel Krebs
93fe1390d6
fix wrong usage of reinterpret_cast in ips and tests
2018-06-04 17:36:36 +02:00
Daniel Krebs
010e0c3681
hls: add base HLS IP and enable virtual multi-inheritance
...
Virtual inheritance is required because (for example) the Rtds2Gpu
IP inherits from Hls and IpNode who both inherit from IpCore.
2018-06-04 17:36:36 +02:00
Daniel Krebs
5c67dc3727
rtds2gpu: update vlnv to match v1.1 and adapt config to new bitstream
2018-06-04 17:36:15 +02:00
Daniel Krebs
28458fdf8a
update rtds2gpu HLS IP to v1.1
...
- better tested IP (testbenches)
- detect invalid frame sizes
- more status reporting
2018-06-04 17:36:15 +02:00
Daniel Krebs
bf286568dd
rtds2gpu IP works
2018-06-04 17:36:15 +02:00
Daniel Krebs
d19619fe1f
tests: cleanup CMakeLists.txt
2018-06-04 14:20:06 +02:00
Daniel Krebs
7bffe82e0e
tests: add (dirty) RTDS test
2018-06-04 14:20:06 +02:00
Daniel Krebs
5097827757
fix include paths, use <villas/...> style
2018-06-04 13:24:57 +02:00
Daniel Krebs
d2384abb9d
cmake: only build GPU library if CUDA is present
2018-05-16 10:58:18 +02:00
Daniel Krebs
13fd3f3c2a
gpu: implement basic GPU plugin that can do DMA to and from its memory
...
Using CUDA, memory can be allocated on the GPU and shared to peers on
the PCIe bus such as the FPGA. Furthermore, the DMA on the GPU can also
be used to read and write to/from other memory on the PCIe bus, such as
BRAM on the FPGA.
2018-05-15 18:15:17 +02:00
Daniel Krebs
24db7ea1c0
tests/dma: update to current progress
2018-05-15 18:04:24 +02:00
Daniel Krebs
8f3833bc73
ips/dma: rename pingpong to memcpy and always connect loopback
2018-05-15 18:04:24 +02:00
Daniel Krebs
3e505c74bf
ips/bram: add block RAM IP and use it with DMA test
2018-04-13 15:35:41 +02:00
Daniel Krebs
5242b87e4c
lib/memory: rework allocators to make them extensible and more abstract
...
This is change renders memory allocators only dependend on an address
space id that they are managing, allowing easy implementation of other
algorithms and instantiation in memory IP blocks.
2018-04-13 15:35:41 +02:00
Daniel Krebs
e28345b992
tests/dma: add test for DMA driver
2018-03-26 16:17:26 +02:00
Daniel Krebs
b01a50184c
kernel/vfio: port to C++
...
This commit is 1/2 of a series of patches and not working on its own.
2018-03-26 16:16:42 +02:00
Daniel Krebs
e66350dbf6
tests: minor fixes in logging
2018-02-14 07:28:25 +01:00
Daniel Krebs
acf273e406
tests: let them fail if no Fifo or Timer is found
2018-02-14 07:27:37 +01:00
Daniel Krebs
95e29f2706
memory-manager: allow for traversing address spaces
...
Major rework of the memory manager. Adds a memory translation class to
resolve addresses across address spaces and extents the memory manager
in order to do so.
2018-02-14 07:27:37 +01:00
Daniel Krebs
7d927155db
tests: minimal test of memory manager
2018-02-14 07:26:39 +01:00
Daniel Krebs
409340433d
enable -Wall, -Wextra and -Werror and fix new errors ( fixes #20 )
2018-02-13 16:04:34 +01:00
8206f867a5
logging: use similar log style in all modules
2018-01-31 20:24:11 +01:00
2336acaf98
tests: override some criteriod_log() functions in order to use spdlog style log output
2018-01-31 20:23:48 +01:00
51a3d0b8e9
tests: some cleanups
2018-01-31 20:22:15 +01:00
2a03d19d53
tests: readd missing graph test suite
2018-01-31 15:12:36 +01:00
b0f4577dd3
tests: automatically detect whether or not we can run tests in parallel
2018-01-31 15:12:19 +01:00
0aed1a1b12
tests: moved initialization of FPGA stuff to fpga.cpp
2018-01-31 15:11:13 +01:00
Daniel Krebs
3de2170ad6
tests: move variables to global state and set criterion jobs to 1
2018-01-31 11:17:21 +01:00
Daniel Krebs
22ce8f2b3f
lib/graph: slightly change interface to allow for custom edges
2018-01-30 19:16:59 +01:00
Daniel Krebs
27c67f206e
lib/graph: add path-finding with loop detection and corresponding unittest
2018-01-30 17:28:42 +01:00
Daniel Krebs
f6c02b8429
lib: add directed graph implementation incl. unittest
2018-01-30 15:13:23 +01:00
daniel-k
e46720d23b
tests: improve logging
2018-01-23 14:43:30 +01:00
daniel-k
62e1a7d962
tests/fifo: fail if connecting loopback doesn't work
2018-01-23 14:43:06 +01:00
daniel-k
21d1dd0a71
tests/timer: test absolute timing
2018-01-16 15:26:19 +01:00
daniel-k
61de103c9e
tests/main: assert that there's an fpga
2018-01-16 15:08:56 +01:00
daniel-k
16455bdd13
tests/fifo: cleanup
2018-01-16 15:08:27 +01:00
daniel-k
e626abfb52
tests/timer: add basic timer test
2018-01-16 15:08:12 +01:00
daniel-k
3cf50db98d
logging: use new spdlog library in favor of Logger
2018-01-10 15:49:53 +01:00
daniel-k
71a54eeab6
lib/ips: implement fifo driver and adapt test
2018-01-10 11:02:08 +01:00
daniel-k
018c89a2b0
tests/main: C++-ify
2018-01-10 11:02:08 +01:00
daniel-k
a5b5e317d4
wip implementing dependency parsing and proper memeory handling
...
works and compiles so for. next is to implement different IP interfaces
(Model, Interface, DataMover, Infrastructure, ...)
2018-01-10 11:02:08 +01:00
