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6d8401d88a
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changing default affinity (some systems only have a single core)
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2016-07-11 16:04:07 +02:00 |
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1516ebab6e
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improved warning messages for affinity
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2016-07-11 16:03:28 +02:00 |
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ecc8e16552
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added better error message in case of invalid config file path
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2016-07-11 16:02:55 +02:00 |
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5320830b13
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added pthread cancelation points to pipe
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2016-07-11 16:02:32 +02:00 |
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0cc67a892c
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improved configuration file parsing
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2016-07-11 11:36:23 +02:00 |
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1669d226c8
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changed config file format for VILLASfpga
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2016-07-11 11:34:20 +02:00 |
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483e9af293
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restructured configuration files
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2016-07-11 11:24:42 +02:00 |
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5f953e4573
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check if libblas and liblapack are present
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2016-07-11 09:17:35 +02:00 |
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cdeed6d5e4
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updated LWS version
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2016-07-11 09:16:47 +02:00 |
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abd8148a2b
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fixed compiler warnings
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2016-07-11 09:16:31 +02:00 |
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bd8987bf35
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simplified makefile
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2016-07-11 09:16:00 +02:00 |
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f9fc56aef9
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added driver for HLS DFT implementation
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2016-07-08 15:25:32 +02:00 |
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a2824d1cf6
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added some shell scripts for FPGA work
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2016-07-08 13:33:47 +02:00 |
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3f012c8575
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finished FPGA stuff
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2016-07-08 13:32:18 +02:00 |
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80fdc6bda8
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finished FPGA tests
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2016-07-08 13:31:46 +02:00 |
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87bd0c3b8c
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reworked interrupt handling
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2016-07-08 13:31:23 +02:00 |
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545ef6fa14
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added documentation to example VILLASfpga config file
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2016-07-08 13:29:42 +02:00 |
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88157a3023
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improved AXI4 switch configuration
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2016-07-08 13:01:40 +02:00 |
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ac389a76ff
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added DMA memory managment functions
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2016-07-08 12:59:09 +02:00 |
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eb7391a4a3
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added LAPACK based benchmark
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2016-07-08 12:56:22 +02:00 |
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fcd07748dd
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fixed partial reads in read_random()
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2016-07-08 12:15:37 +02:00 |
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87eb7c13e2
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removed obsolete BRAM IP driver
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2016-07-08 12:14:54 +02:00 |
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27bf41d03e
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some smaller changes to Makefile
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2016-06-26 15:35:08 +02:00 |
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f413355d05
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updated the configuration
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2016-06-26 15:34:40 +02:00 |
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05af02304d
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added a couple of functions to parse and print cpu_set_t
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2016-06-26 15:33:59 +02:00 |
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a22ec73c06
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some new benchmarks and tests for VILLASfpga
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2016-06-26 15:33:19 +02:00 |
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def9d0ec6d
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code cleanup for pipe tool
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2016-06-26 15:33:04 +02:00 |
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fd525e5701
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added log init to signal generator
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2016-06-26 15:32:37 +02:00 |
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79b35dafdf
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fixed typo in Xilinx code
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2016-06-26 15:32:06 +02:00 |
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d811128459
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added support for dynamically loaded plugins
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2016-06-26 15:31:31 +02:00 |
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238c732feb
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smaller fixes in linux code
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2016-06-26 15:29:07 +02:00 |
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cc66553761
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added support for CBuilder models
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2016-06-26 15:28:34 +02:00 |
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132dd5fd65
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moved linux realtime code to extra file
|
2016-06-26 15:27:14 +02:00 |
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68f2dbea76
|
major changes in the VILLASfpga code. Lots of smaller improvements and fixed
|
2016-06-26 15:22:25 +02:00 |
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c67af15a2c
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fixed all major bugs in FPGA code
|
2016-06-19 19:30:00 +02:00 |
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98fb370e85
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first steps towards flexible and configurable VILLASfpga / VILLASnode integration
|
2016-06-15 20:05:09 +02:00 |
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bffb47dca8
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added VILLASfpga code
|
2016-06-14 01:23:44 +02:00 |
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0fa5f5b976
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introduced new directory structure for source and header files
|
2016-06-14 01:17:58 +02:00 |
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d589c71ab6
|
missed something to rename
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2016-06-13 21:44:39 +02:00 |
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35bfd02b13
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added debug facilities to debug output
|
2016-06-13 21:43:08 +02:00 |
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04aad098bb
|
fixed some whitespace
|
2016-06-13 21:41:55 +02:00 |
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43cee1184b
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fixed image url
|
2016-06-13 21:33:26 +02:00 |
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5ffb16ec8f
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fixed unclosed file
|
2016-06-13 17:27:32 +02:00 |
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277589029e
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fixed collision of procprocessor macro
|
2016-06-13 17:25:09 +02:00 |
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f635bf115a
|
fixed argument type for integer_to_cpuset
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2016-06-13 17:25:09 +02:00 |
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f3951afd18
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added ability to pin IRQs
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2016-06-13 17:25:09 +02:00 |
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c53cb80f42
|
started working on new gtfpga node-type
|
2016-06-13 17:23:33 +02:00 |
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9096de8024
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fixed broken nags node-type
|
2016-06-08 23:42:44 +02:00 |
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ad8ee1c3f7
|
renamed S2SS to VILLASnode
|
2016-06-08 23:31:58 +02:00 |
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af6af5bb76
|
fixed renamed file
|
2016-06-08 22:54:13 +02:00 |
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