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6337 commits

Author SHA1 Message Date
6d8401d88a changing default affinity (some systems only have a single core) 2016-07-11 16:04:07 +02:00
1516ebab6e improved warning messages for affinity 2016-07-11 16:03:28 +02:00
ecc8e16552 added better error message in case of invalid config file path 2016-07-11 16:02:55 +02:00
5320830b13 added pthread cancelation points to pipe 2016-07-11 16:02:32 +02:00
0cc67a892c improved configuration file parsing 2016-07-11 11:36:23 +02:00
1669d226c8 changed config file format for VILLASfpga 2016-07-11 11:34:20 +02:00
483e9af293 restructured configuration files 2016-07-11 11:24:42 +02:00
5f953e4573 check if libblas and liblapack are present 2016-07-11 09:17:35 +02:00
cdeed6d5e4 updated LWS version 2016-07-11 09:16:47 +02:00
abd8148a2b fixed compiler warnings 2016-07-11 09:16:31 +02:00
bd8987bf35 simplified makefile 2016-07-11 09:16:00 +02:00
f9fc56aef9 added driver for HLS DFT implementation 2016-07-08 15:25:32 +02:00
a2824d1cf6 added some shell scripts for FPGA work 2016-07-08 13:33:47 +02:00
3f012c8575 finished FPGA stuff 2016-07-08 13:32:18 +02:00
80fdc6bda8 finished FPGA tests 2016-07-08 13:31:46 +02:00
87bd0c3b8c reworked interrupt handling 2016-07-08 13:31:23 +02:00
545ef6fa14 added documentation to example VILLASfpga config file 2016-07-08 13:29:42 +02:00
88157a3023 improved AXI4 switch configuration 2016-07-08 13:01:40 +02:00
ac389a76ff added DMA memory managment functions 2016-07-08 12:59:09 +02:00
eb7391a4a3 added LAPACK based benchmark 2016-07-08 12:56:22 +02:00
fcd07748dd fixed partial reads in read_random() 2016-07-08 12:15:37 +02:00
87eb7c13e2 removed obsolete BRAM IP driver 2016-07-08 12:14:54 +02:00
27bf41d03e some smaller changes to Makefile 2016-06-26 15:35:08 +02:00
f413355d05 updated the configuration 2016-06-26 15:34:40 +02:00
05af02304d added a couple of functions to parse and print cpu_set_t 2016-06-26 15:33:59 +02:00
a22ec73c06 some new benchmarks and tests for VILLASfpga 2016-06-26 15:33:19 +02:00
def9d0ec6d code cleanup for pipe tool 2016-06-26 15:33:04 +02:00
fd525e5701 added log init to signal generator 2016-06-26 15:32:37 +02:00
79b35dafdf fixed typo in Xilinx code 2016-06-26 15:32:06 +02:00
d811128459 added support for dynamically loaded plugins 2016-06-26 15:31:31 +02:00
238c732feb smaller fixes in linux code 2016-06-26 15:29:07 +02:00
cc66553761 added support for CBuilder models 2016-06-26 15:28:34 +02:00
132dd5fd65 moved linux realtime code to extra file 2016-06-26 15:27:14 +02:00
68f2dbea76 major changes in the VILLASfpga code. Lots of smaller improvements and fixed 2016-06-26 15:22:25 +02:00
c67af15a2c fixed all major bugs in FPGA code 2016-06-19 19:30:00 +02:00
98fb370e85 first steps towards flexible and configurable VILLASfpga / VILLASnode integration 2016-06-15 20:05:09 +02:00
bffb47dca8 added VILLASfpga code 2016-06-14 01:23:44 +02:00
0fa5f5b976 introduced new directory structure for source and header files 2016-06-14 01:17:58 +02:00
d589c71ab6 missed something to rename 2016-06-13 21:44:39 +02:00
35bfd02b13 added debug facilities to debug output 2016-06-13 21:43:08 +02:00
04aad098bb fixed some whitespace 2016-06-13 21:41:55 +02:00
43cee1184b fixed image url 2016-06-13 21:33:26 +02:00
5ffb16ec8f fixed unclosed file 2016-06-13 17:27:32 +02:00
277589029e fixed collision of procprocessor macro 2016-06-13 17:25:09 +02:00
f635bf115a fixed argument type for integer_to_cpuset 2016-06-13 17:25:09 +02:00
f3951afd18 added ability to pin IRQs 2016-06-13 17:25:09 +02:00
c53cb80f42 started working on new gtfpga node-type 2016-06-13 17:23:33 +02:00
9096de8024 fixed broken nags node-type 2016-06-08 23:42:44 +02:00
ad8ee1c3f7 renamed S2SS to VILLASnode 2016-06-08 23:31:58 +02:00
af6af5bb76 fixed renamed file 2016-06-08 22:54:13 +02:00