This patch removes compilation errors by enabling the
IntelStmFlashInitialize function for STM flash family
on DC1.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies xil_mpu.c to add the API Xil_SetMPURegion
which provide the settings for a MPU region with size
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Specify the format attribute for the xil_printf() function to allow the
compiler to do printf-style checking of the format string and arguments.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'p' conversions as alias of 'x'. Strictly, not fully correct, but
better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'X' conversions as alias of 'x'. Strictly, that is not fully
correct, but still better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Xil_DCacheDisable() function internally has call to Xil_DCacheFlush().
Hence removing redundant calls to Xil_DCacheFlush from FSBL.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Exception handlers are now registered unconditionally for both A53 and R5
Removed enabling of IRQ from FSBL(to be enabled in user application)
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch modifies translation_table.S to put check whether
the DDR is present or not to fix the compilation error in
case of DDR-less system
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch removes xmpu, slcr, xppu header files from cortexr5 folder
and standalone tcl has been modified to copy the header files from
cortexa53/includes_ps. Makefile has been modified to include the
header files in include folder while compilation
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch creates folder 64bit to accomodate cortex-a53 64bit
mode BSP files and creates another folder includes_ps for
xmpu, xppu, slcr header files. It also changes the standalone tcl to
reflect the necessary changes
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies the check for whether bank crossover
in flash read functions for parallel case. This will fix
the bug where wrap around occurs to the top of flash when
reading very bottom..
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Check for card detection only if that signal is present
(based on HAS_CD macro)
Signed-off-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Harini Katakam <harinik@xilinx.com>
While creating new FSBL+BSP project, made xilsecure library
to be selected by default. This avoids compilation errors
when FSBL project is created.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
The makefile tries to detect gnu vs ARM toolchain by string-comparing
the COMPILER with some hardcoded values. This fails when the toolchain
is specified with directory components. Hence, remove directory
components from the tests.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
When authentication of partitions is not enabled, decryption is failing.
This patch fixes this issue.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch does the changes in FSBL to match the signature changes of
few functions in xilsecure library.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
