Modified cortexr5/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS correctly.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
to update ECC_FLAGS to fix a bug introduced during new version creation
of BSP
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies xil_settlbattributes API to work with
addresses > 4GB by modifying the address masking value
appropriate for higher addresses lies beyond 4GB
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies the makefile for a53 to take the compiler and
archiver name from cpu tcl rather than fixing them.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies the makefile for r5 to take the compiler and
archiver name from cpu tcl rather than fixing them.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil_printf to add support for 64bit
pointer value print in case of 64bit mode. It adds support
to print 64 bit value for long integer and long hex.
It also removes unknown specifier 'D'.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil_mpu.c to add the API Xil_SetMPURegion
which provide the settings for a MPU region with size
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Specify the format attribute for the xil_printf() function to allow the
compiler to do printf-style checking of the format string and arguments.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'p' conversions as alias of 'x'. Strictly, not fully correct, but
better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Treat 'X' conversions as alias of 'x'. Strictly, that is not fully
correct, but still better than ignoring them.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies xil-crt0.S to remove Init_Uart API call
as fsbl is initializing the UART
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies translation_table.S to put check whether
the DDR is present or not to fix the compilation error in
case of DDR-less system
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch removes xmpu, slcr, xppu header files from cortexr5 folder
and standalone tcl has been modified to copy the header files from
cortexa53/includes_ps. Makefile has been modified to include the
header files in include folder while compilation
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch creates folder 64bit to accomodate cortex-a53 64bit
mode BSP files and creates another folder includes_ps for
xmpu, xppu, slcr header files. It also changes the standalone tcl to
reflect the necessary changes
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
