Read specific status register for negotiated speed and return the same.
The updated masks are only used for ZynqMP currently; follow the same
for Zynq as well. Corrected alignment in a couple of lines.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Bootgen currently has no support for multiple loadable sections
in elfs. So a workaround is being implemented in PMUFW linker
script. All sections are forced to be loadable and dummy bytes
are added to fill the gaps. This change causes linker to throw
a warning about bss section being made PROGBITS.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
This patch removes alignment for local variables
which is not necessary.Iar compiler does not allow
alignment to local variables.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Changed the format specifiers from %x to %lx and %d to %lu
while printing unsigned long variables.
Without these changes many warnings are shown in FSBL when xil_printf
type in BSP is changed to be compatible with printf.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch modifies ipi_isr in baremetal.c to make it compatible
with freertos supported openamp library.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch modifies ipi_isr in baremetal.c to make it compatible
with freertos supported openamp library.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Currently for R5, compiler flag for, floating-point ABI is mentioned
as "softfp". This causes abort on encountering floating point arithmetic
operation. Hence changing this flag to "soft".
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
Add support for A53:
- Add __aarch64__ in conditional compilation
- Disable data cache as lwip is not working on A53 with caches enabled
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
- Update mac address form s32 to u32
- Update autonegotiation for ZynqMP when checking status register for
negotiated speed. Report error when autonegotiation has failed for ~30 secs.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Add support for A53 by doing the following:
- Update conditional checks with __aarch64__
- Update typecast to UINTPTR
- Update u32_t type
- Update debug prints to reflect 64 bit address
- Disable data cache as lwip is not working on A53 with caches at the moment
- Update changelog for previouos missing history as well
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
For 64 bit address, upper 32 bits should be updated in respective
TX and RX queue pointer registers. For tx, typecast with u32 should not
be there; remove it. For rx, update the correspondign register.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
This patch modifies the SPIPS examples to support on
ZynqMP. In Zynq we are selecting hardware using chip
select 0 where as 1 in ZynqMP and also we will use
two different interrupt id's in two platforms.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add polled and interrupt examples to test
QSPIPSU flash interface.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add QSPIPSU flash interface support
in ZynqMP.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add support for spips peripheral
for ZynqMP in tcl file.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add qspipsu peripheral support in
tcl file.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This fix enables the compiler flags specified in HSI command line
to be appended to those specified in FSBL tcl file.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
- Renamed xhdcp1x_cipher_hw.h to xhdcp1x_hw.h
- Moved low-level macros to the new xhdcp1x_hw.h file.
- Included xhdcp1x_hw.h in xhdcp1x.h, exposing register definitions
to the user.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
- Macros to follow format of other drivers.
- Raw read and writes act upon the base address.
- Removed IsTX, IsRX, IsHDMI, and IsDP since these macros were acting
on the software and there are already associated macros for checking
the hardware. To remove confusion InstancePtr->Config.Is* is used
instead.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
Initialization functions for the cipher, port, and directions are now invoked
from within the XHdcp1x_CfgInitialize function directly.
No need to do check for inconsistencies between HW and SW for protocol and
direction because this scenario will never happen unless SDK generates the
xparameters.h incorrectly. The self test is the more appropriate place for this
check.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
The way the CfgPtr is now consistent with the rest of the drivers.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Shadul Shaikh <shaduls@xilinx.com>
