This patch modifies asm_vectors.s and xil_exception.c to print the
address for instruction causing data abort and prefetch abort in
default handler
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies Xil_DCacheInvalidateRange and Xil_DCacheFlushRange
to remove unnecessary dsb in the APIs. It also adds necessary
Xil_L2CacheSync in Xil_L2CacheInvalidateRange API.
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch changes the initialization order in boot.S to follow
the correct order as specified in CortexA9 TRM
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Added interlaced and progressive mode switching functionality.
Removed XVtc_RegUpdate as there were 2 APIS with same functionality
provided backward compatibility.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Corresponding fields in the devcfg.STATUS register are written to,
for clearing DMA done count.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch initialises RSAKeyReadback value with zero's since
if RSA key is read with XSK_EFUSEPS_ENABLE_RSA_KEY_HASH as FALSE
then it will return zero.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies files to fix warnings that got
generated when -Wextra flag was used.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
when -d option is used to dump all the registers,
It should ignore the Data register if it's empty or
Not set and should not return a failure in reading those registers.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch adds the "Type" option of (b or h or w)
for the -c option when the help menu is printed.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch removes alignment for buffers since cacheInvalidate will
take care of it and made few MISRAC changes.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch removes alignment for Buffers since cacheInvalidate will
take care of it and used cacheInvalidate API instaed of cacheFlush
in changeBusSpeed API.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Previously, INTERRUPT_CAUSE bits 8 to 31 were being lost due to the variables
assigned having type u8.
This fix now uses masking on the interrupts as the condition to run an interrupt
handler rather than assigning the mask result to a new variable and using the
variable as a boolean condition.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This patch fixes the compilation errors
during generation of lwip echo server app
when axi ethernet is configured with AXI4-Stream
Data FIFO.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This patch modifies standalone.tcl, A53 gcc makefile and
R5 gcc makefile such that profiling support for these
A53/R5 bsps was removed.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch modifies standalone.tcl for supporting psu_microblaze
and also pss_* notation was replaced to psu_*.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This patch removes IAR compilation error in example by removing
the u32 typecast since it is expecting (void *)
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch removes the IAR compilation errors.
Modified the OnfiNand_Geometry structure declaration according to IAR compiler
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Bit 21 of DPTX register PHY_CONFIG (0x200) enables 8b10b encoding.
In v6.0 of the DPTX core, the default value is '1'.
Current driver should keep this value untouched when writing to the PHY_CONFIG
register.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Bit 21 of DPTX register PHY_CONFIG (0x200) enables 8b10b encoding.
In v6.0 of the DPTX core, the default value is '1'.
Current driver should keep this value untouched when writing to the PHY_CONFIG
register.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This patch modifies the function signature of lseek
to compile on ICC ARM compiler.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
