This patch does following things
1. Added IO mode support for qspipsu.
2. Modified the GenFifoEntryData API since unaligned data should
be the last entry in GenFifo.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Ensure that the dma buffer boundary interrupt is disabled as driver
is using the contiguous buffer for the whole page size and enabling
this interrupt would cause failures if the buffer boundary is
configured for other values (not the page size)
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
This is the first functional set of files with
-Power Management
-Error Handlers
-Basic Timer based Scheduler
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Made changes in FSBL tcl file so that unnecessary files are deleted
from build. Since HSI and SDK create their own Makefile,
static Makefile is also removed from build. Also based on CPU,
compiler optins are set to match to those set in SDK.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
FSBL has R5 specific behaviours so -mcpu must be passed to the build.
Automatically do this on app generation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Adding this feature in FSBL enables BootROM to search for
next available image in the boot devices. Also user can
jump to a different image with the help of multiboot.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
While releasing resets, power on reset bit fields of
the corresponding CPU core also considered now.
These bit fields are added in RST_FPD_APU register from RTL 5.0.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Added interlaced and progressive mode switching functionality.
Removed XVtc_RegUpdate as there were 2 APIS with same functionality
provided backward compatibility.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Signature for function f_mount() is changed.
Now three arguments are expected (earlier had two arguments).
In FSBL code, now f_mount() is called with new set of arguments.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch removes the IAR compilation errors.
Modified the OnfiNand_Geometry structure declaration according to IAR compiler
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Modified driver source file to remove compiler warning.
1. Did Type Conversion
2. Made two API's public
3. Removed redeclaration
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
HSI API is now also generating PMU configuration source file
which is not needed in FSBL. Hence deleting it.
Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com>
Bit 21 of DPTX register PHY_CONFIG (0x200) enables 8b10b encoding.
In v6.0 of the DPTX core, the default value is '1'.
Current driver should keep this value untouched when writing to the PHY_CONFIG
register.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This patch changes to psu from pss for processor instance to create
CPU ID in xparameters.h
Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This patch modifies eeprom start address in polled example and
updated the note in header in repeated start example.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch implemented the large data transfer using repeated
start in Zynq Ultra Scale MP and fixed doxygen warnings.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This initial version has the basic set of files required to
build a basic firmware for PMU Microblaze in ZynqMP
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
This patch added check for SLCR lock before doing the SLCR
reset. If it is unlocked we ahould not lock after reset.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Kept only psu_nand as supported_peripherals for Zynq UltraScale MP Generic
NAND controller driver.
Removed pss_nand and ps8_nand from supported_peripherals.
Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
This patch changes the peripheral name notation from
pss_csudma to psu_csudma. Also removes ps8_csudma.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
