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77 commits

Author SHA1 Message Date
Andrei-Liviu Simion
fdc058a91a dp: tx: Register space has 3 hex digits. 
Clean-up.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:34:29 +05:30
Andrei-Liviu Simion
1a280fdfc7 dp: Unified naming of xdptx and xdprx to xdp. 
As per Xilinx standalone coding guidelines.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:34:21 +05:30
Andrei-Liviu Simion
4d686c08e0 dp: Check for ARM first for usleep. 
Zynq systems may have both MicroBlaze and ARM. If this is the case, assume that
the application is running on an ARM processor.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:34:03 +05:30
Andrei-Liviu Simion
aa72195688 dp: rx: Use definitions instead of hard-coded values. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:34:02 +05:30
Andrei-Liviu Simion
01658a8c12 dp: rx: Updated some of the modification history. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:34:01 +05:30
Andrei-Liviu Simion
37dd178424 dp: rx: Fixed names of some incorrectly used definitions. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:34:00 +05:30
Andrei-Liviu Simion
574034b189 dp: rx: Added selftest function. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:59 +05:30
Andrei-Liviu Simion
e0d0e0c1e7 dp: rx: Added core masks, shifts, and register values. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:57 +05:30
Andrei-Liviu Simion
178a11326e dp: rx: Added assertions on function arguments. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:56 +05:30
Andrei-Liviu Simion
835c8acbab dp: rx: Added modification history. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:56 +05:30
Andrei-Liviu Simion
249af540c6 dp: rx: Added file header documentation. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:55 +05:30
Andrei-Liviu Simion
ff3f15acbb dp: rx: Added function header comments for interrupt related functions. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:54 +05:30
Andrei-Liviu Simion
9463358c28 dp: rx: Added function header comments for primary source file. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:53 +05:30
Andrei-Liviu Simion
13e6880ff5 dp: rx: Added a function to enable a specified interrupt. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:51 +05:30
Andrei-Liviu Simion
3748170590 dp: rx: Added a function to disable a specified interrupt. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:51 +05:30
Andrei-Liviu Simion
8593e4f84a dp: rx: Added a function to generate an HPD. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:50 +05:30
Andrei-Liviu Simion
f588c504e9 dp: rx: Added interrupt handler. 
The interrupt handler arbitrates interrupts to appropriate handlers.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:49 +05:30
Andrei-Liviu Simion
7f0b844897 dp: rx: Fixed naming of interrupt handlers. 
Mislabeled TX instead of RX.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:48 +05:30
Andrei-Liviu Simion
de3fbb4466 dp: rx: Added callback for training pattern interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:47 +05:30
Andrei-Liviu Simion
1b613594e3 dp: rx: Added callback for bandwidth change interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:46 +05:30
Andrei-Liviu Simion
26829905a9 dp: rx: Added callback for training done interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:46 +05:30
Andrei-Liviu Simion
134b32d770 dp: rx: Added callback for valid video interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:45 +05:30
Andrei-Liviu Simion
937ccc287c dp: rx: Added callback for training lost interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:44 +05:30
Andrei-Liviu Simion
fba443ffde dp: rx: Added callback for vertical blanking interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:43 +05:30
Andrei-Liviu Simion
2a79d28de6 dp: rx: Added callback for no video interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:42 +05:30
Andrei-Liviu Simion
c5b9fdac16 dp: rx: Added callback for power state change interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:41 +05:30
Andrei-Liviu Simion
bdc15ffdfe dp: rx: Added callback for video mode change interrupts. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:41 +05:30
Andrei-Liviu Simion
a94f816019 dp: rx: Added function to check the link status on all lanes. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:40 +05:30
Andrei-Liviu Simion
0e0e170875 dp: rx: Added function to set the user pixel width. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:39 +05:30
Andrei-Liviu Simion
3b2d898c44 dp: rx: Added function to override the DPCD lane count value. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:38 +05:30
Andrei-Liviu Simion
26bdc1bd63 dp: rx: Added function to override the DPCD link rate value. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:37 +05:30
Andrei-Liviu Simion
36aa085a0e dp: rx: Added register values to override the lane count. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:36 +05:30
Andrei-Liviu Simion
aa7172ded9 dp: rx: Added register values for overriding the link rate. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:35 +05:30
Andrei-Liviu Simion
3736bcbce0 dp: Reordered the listing of initialization functions. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:34 +05:30
Andrei-Liviu Simion
c80bd4b59d dp: rx: Increased the time to wait for the PHY to be ready. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:34 +05:30
Andrei-Liviu Simion
ccfd95487f dp: rx: Added core initialization. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:33 +05:30
Andrei-Liviu Simion
6ba1a4e305 dp: rx: Added interrupt masks. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:31 +05:30
Andrei-Liviu Simion
3465d04239 dp: rx: Added a function to disable the display timing generator. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:30 +05:30
Andrei-Liviu Simion
f5c0d7b518 dp: rx: Added a function to enable the display timing generator. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:30 +05:30
Andrei-Liviu Simion
5d03fa54da dp: rx: Added function to wait for the PHY to be ready. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:29 +05:30
Andrei-Liviu Simion
bd16c255da dp: rx: Added timer functionality. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:28 +05:30
Andrei-Liviu Simion
b3a492d02a dp: rx: Added link configuration structure. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:27 +05:30
Andrei-Liviu Simion
73e9f13cea dp: tx: Updated selftest since usage of some defines now take an argument. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:26 +05:30
Andrei-Liviu Simion
b59cb36747 dp: rx: Added vendor specific DPCD registers. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:25 +05:30
Andrei-Liviu Simion
8933949ee9 dp: rx: Added MST sideband messaging registers. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:24 +05:30
Andrei-Liviu Simion
1cb3119c90 dp: rx: Added MST MSA offsets for streams 2, 3, and 4. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:23 +05:30
Andrei-Liviu Simion
6157f90f4d dp: rx: Added MSA registers. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:22 +05:30
Andrei-Liviu Simion
88d0e95839 dp: rx: Added DPCD configuration space registers. 
These are read-only values that represent the corresponding fields of the RX's
DPCD as seen by the TX.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:21 +05:30
Andrei-Liviu Simion
e6f4d82a4f dp: rx: Added audio registers. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:21 +05:30
Andrei-Liviu Simion
c61b1b58d5 dp: rx: Added PHY configuration and status registers. 
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
 2015-04-26 10:33:19 +05:30