cb2b980567
updated FPGA docs (not complete yet)
2016-08-29 00:07:38 -04:00
Markus Grigull
9dddebad6f
Add deployment graphic
2016-08-16 13:06:43 +02:00
608c8a6fb3
remove Travis image
2016-08-14 22:00:12 +02:00
8aef33ca7b
change S2SS -> VILLASndoe
2016-08-14 21:58:54 +02:00
Umar Farooq
62bf0c2b0c
Bug fixes/improvements to GTNET-SKT code
...
- Change enum types APP_HDR_* to SOCKET_HDR_*
- Remove SOCKET_HDR_NONE type from app-hdr as its same as
SOCKET_HDR_GTSKT
- Fix values per samples for GTSKT to 1
- Replace TODO tag with @todo
- Use SOCKET_HDR_DEFAULT if app_hdr setting is not present
in config file
- Fix bug when invalid message is received resulting in
infinite printing loop
- Fix bug in socket_write when due to declaration of struct
msg msgs[cnt] in the for loop the values are not transmitted
- Replace std=c98 with std=c11 but still compile without it
2016-08-02 21:08:25 +02:00
5655681807
improved Makefile for plugins
2016-07-26 22:07:37 +02:00
7f4f898b70
fixed compiler warnings about uninitialized use
2016-07-26 15:42:11 +02:00
7017ececce
updated title in readme
2016-07-26 12:55:09 +02:00
f6dd0b117b
merged config-fpga.h into config.h
2016-07-18 15:09:49 +02:00
303e730f3a
removed debug output
2016-07-18 15:02:53 +02:00
83231872cf
fixed WebSocket support in Makefile
2016-07-18 15:01:14 +02:00
Umar Farooq
2f47be0ac5
Add app_hdr tag for GT-NET-Socket
...
GT-NET-Socket uses a tag in the config file to distinguish from default
socket node type application layer header (struct msg). For now all the
values are encoded in the struct sample without any header (no timestamp
or sequence number).
Minor improvement in pipe.c: replace 'goto' with do while
2016-07-17 01:01:43 +02:00
5d725957b8
finalizing CBuilder example and documentation
2016-07-15 12:28:28 +02:00
812eb31c95
cleaning function namespaces: config_ => cfg
2016-07-14 09:47:00 +02:00
cbe29caf98
restructured repo and build system
2016-07-14 09:34:26 +02:00
899e07aa9a
fixed web socket JS
2016-07-12 12:47:50 +02:00
9f9407c3d3
tweaked Oxygen HTML output
2016-07-12 10:44:52 +02:00
23c5bb1df3
tweaked WebSocket Web Layout
2016-07-12 10:44:20 +02:00
8e255cf083
added new web socket HTML / JS code and new logo
2016-07-11 18:19:48 +02:00
3880abeb63
unified member variable naming of struct sample and struct msg
2016-07-11 18:19:23 +02:00
8115a9caa2
fixed most major bugs of web socket node-type
2016-07-11 18:18:20 +02:00
6d8401d88a
changing default affinity (some systems only have a single core)
2016-07-11 16:04:07 +02:00
1516ebab6e
improved warning messages for affinity
2016-07-11 16:03:28 +02:00
ecc8e16552
added better error message in case of invalid config file path
2016-07-11 16:02:55 +02:00
5320830b13
added pthread cancelation points to pipe
2016-07-11 16:02:32 +02:00
0cc67a892c
improved configuration file parsing
2016-07-11 11:36:23 +02:00
1669d226c8
changed config file format for VILLASfpga
2016-07-11 11:34:20 +02:00
483e9af293
restructured configuration files
2016-07-11 11:24:42 +02:00
5f953e4573
check if libblas and liblapack are present
2016-07-11 09:17:35 +02:00
cdeed6d5e4
updated LWS version
2016-07-11 09:16:47 +02:00
abd8148a2b
fixed compiler warnings
2016-07-11 09:16:31 +02:00
bd8987bf35
simplified makefile
2016-07-11 09:16:00 +02:00
f9fc56aef9
added driver for HLS DFT implementation
2016-07-08 15:25:32 +02:00
a2824d1cf6
added some shell scripts for FPGA work
2016-07-08 13:33:47 +02:00
3f012c8575
finished FPGA stuff
2016-07-08 13:32:18 +02:00
80fdc6bda8
finished FPGA tests
2016-07-08 13:31:46 +02:00
87bd0c3b8c
reworked interrupt handling
2016-07-08 13:31:23 +02:00
545ef6fa14
added documentation to example VILLASfpga config file
2016-07-08 13:29:42 +02:00
88157a3023
improved AXI4 switch configuration
2016-07-08 13:01:40 +02:00
ac389a76ff
added DMA memory managment functions
2016-07-08 12:59:09 +02:00
eb7391a4a3
added LAPACK based benchmark
2016-07-08 12:56:22 +02:00
fcd07748dd
fixed partial reads in read_random()
2016-07-08 12:15:37 +02:00
87eb7c13e2
removed obsolete BRAM IP driver
2016-07-08 12:14:54 +02:00
27bf41d03e
some smaller changes to Makefile
2016-06-26 15:35:08 +02:00
f413355d05
updated the configuration
2016-06-26 15:34:40 +02:00
05af02304d
added a couple of functions to parse and print cpu_set_t
2016-06-26 15:33:59 +02:00
a22ec73c06
some new benchmarks and tests for VILLASfpga
2016-06-26 15:33:19 +02:00
def9d0ec6d
code cleanup for pipe tool
2016-06-26 15:33:04 +02:00
fd525e5701
added log init to signal generator
2016-06-26 15:32:37 +02:00
79b35dafdf
fixed typo in Xilinx code
2016-06-26 15:32:06 +02:00
