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Commit graph

614 commits

Author SHA1 Message Date
add8dad95b remove useless includes 2022-10-28 08:06:57 -04:00
894460cd7b intc: fix VLNV for Niklas' new bistream 2022-10-28 08:05:48 -04:00
2d21432a5f aurora: fix names of AXI-S interfaces 2022-10-28 08:05:30 -04:00
0e0197a3be fix coding style 2022-10-28 08:03:57 -04:00
7ccb23d8b4 remove old C code 2022-10-28 02:18:21 -04:00
72cfade589 dma: start implementing scatter-gather support 2022-10-27 06:02:45 -04:00
26231dc78c add example config for VILLASnode integration 2022-10-27 06:02:20 -04:00
2ad5fc1ccf remove broken symlink 2022-10-27 06:01:55 -04:00
80abbb866b add latest vc707 config 2022-10-27 06:01:42 -04:00
b37388a143 remove last pieces of hardware submodule 2022-10-13 03:38:39 -04:00
7ceffa642b bump libxil version requirement 2022-09-13 03:31:38 -04:00
60df06113e villas-fpga-pipe: whitespaces and syntax fixes 2022-09-13 03:25:48 -04:00
0a93da7bad adjust DMA IP core to new DMA parameters of Niklas' bitstream 2022-09-13 03:25:17 -04:00
161a9e349f update VILLAScommon submodule 2022-08-30 12:22:40 -04:00
d6c7e69866 add missing parentheses 2022-08-30 12:22:40 -04:00
9ef01d068e update year in copyright notices 2022-08-30 12:22:40 -04:00
c7180e729a fixes for villas-fpga-pipe 2022-08-30 12:22:36 -04:00
fb824a82f9 cleanup of comments 2022-08-30 12:21:46 -04:00
5c68a22ffe add new IP core for standard Xilinx Aurora cores 2022-08-30 12:21:46 -04:00
8a6832edc3 card: allow loading IPs devicetree from extra file 2022-08-30 12:21:46 -04:00
0597e975a0 update gitignore 2022-08-30 12:21:46 -04:00
a433ba5d44 add VSCode configuration for GDB debugging as root 2022-08-30 12:21:46 -04:00
f2a1c78f96 harmonize logger names 2022-08-30 12:21:45 -04:00
bcec3efd5f update code to latest common submodule 2022-08-30 12:21:45 -04:00
28262ef79b remove old configs 2022-08-30 12:21:45 -04:00
b202f11d05 update hardware submodule 2022-08-30 12:21:45 -04:00
7e3a58ce2e update gitignore 2022-08-30 16:36:01 +02:00
8beac4a394 fix CI 2022-03-04 03:46:47 -05:00
c90b1c1f3e fix format strings 2022-03-04 03:33:47 -05:00
8a99307ba2 update config include 2022-03-04 03:33:27 -05:00
49572d0a74 adapt to new plugin registry 2022-03-04 03:33:07 -05:00
53c4c4bf77 remove obsolete htdocs setting 2022-03-04 03:30:42 -05:00
8d6e9eda5d remove hardware submodule 2021-07-07 12:31:33 +02:00
f59a763cd1 Merge branch 'fix-cmake' into 'master'
cmake: allow linking libxil from non-standard location

See merge request acs/public/villas/fpga/fpga!15
2020-11-12 00:45:06 +01:00
2bbe5bc0ab cmake: allow linking libxil from non-standard location 2020-11-12 00:19:55 +01:00
a04c1d7abf ci: add cppcheck 2020-09-21 09:37:10 +02:00
5502d3577b remove unused submodules 2020-08-17 17:21:18 +02:00
8ec16094f2 fix code-style 2020-07-27 16:48:53 +02:00
e5545aa17e emc: add initial code to flash FPGA bitstream via PCIe 2020-07-08 17:16:43 +02:00
eabae63714 update submodules 2020-07-08 15:24:01 +02:00
08114652d6 emc: add stub IP 2020-07-08 15:20:05 +02:00
10b8878279 fix naming of factories 2020-07-08 15:10:26 +02:00
8bb033f89d update hardware submodule and move hwdef-parse script into hardware repo 2020-07-08 14:14:38 +02:00
Hatim Kanchwala
8a4e95d75c Use sensible colour scheme for error status output 2020-07-04 15:11:01 +02:00
Hatim Kanchwala
89f75c9a57 Remove old JSON config files 2020-07-04 15:11:00 +02:00
c4fe7e4b07 update libxil submodule 2020-06-15 22:49:43 +02:00
ba9d670d4b cmake: make unit-tests optional 2020-06-15 22:49:19 +02:00
7e2365bfa0 ci: update CI config 2020-06-15 22:09:18 +02:00
031311ba95 docker: add missing deps 2020-06-15 21:45:50 +02:00
a935a5856a docker: add mising ssl headers 2020-06-15 21:29:46 +02:00