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614 commits

Author SHA1 Message Date
2700493f2f docker: fix location of FEIN e.V. repo 2020-06-15 21:25:55 +02:00
c5e3d3dd4a node: add connect() with reverse path 2020-06-15 21:21:16 +02:00
6c225c8fae update VILLAScommon submodule 2020-06-15 21:21:05 +02:00
74f55fa98c refactor: more code-style improvements 2020-06-15 21:08:49 +02:00
cc456b6525 refactor: no namespace scopes in source files 2020-06-14 22:12:41 +02:00
d938bd95b1 cmake: fixups for inclusion into VILLASnode 2020-06-14 22:11:58 +02:00
a9f9dc4a37 refactor: no namespace scoeps in source files 2020-06-14 22:11:26 +02:00
8b7bbe27c6 refactor: whitespaces for references 2020-06-14 22:03:50 +02:00
e86a291dfd update VILLAScommon submodule 2020-06-12 00:08:04 +02:00
6b3164dd26 refactor IpNode and IpCore class names 2020-06-12 00:05:03 +02:00
7c92a30ab4 several cleanups and bugfixes 2020-06-11 23:55:05 +02:00
bb8a711f02 use new getter for graph 2020-06-11 23:40:12 +02:00
1af96b20e4 pipe: use correct DMA instance 2020-06-11 19:02:49 +02:00
b7e5bfead2 harmonize codestyle 2020-06-11 18:38:46 +02:00
3f1ab8e862 use new vlnv id for aurora_axis 2020-06-11 18:19:28 +02:00
77b55f65f7 use new plugin mechanism 2020-06-11 18:19:03 +02:00
91f9000038 unit-tests: allow FPGA configuration to provided via env var 2020-06-11 16:09:58 +02:00
cc1d1d4298 plugin: fix lookup 2020-06-11 16:01:42 +02:00
86f8997b05 gpio: add new IP for AXI programmable GPIO 2020-06-11 15:58:02 +02:00
d5b1012b75 intc: fix name of register space 2020-06-11 15:57:05 +02:00
6882e9d418 harmonize code-style with VILLAScommon/node 2020-06-11 14:26:38 +02:00
c906116d86 update to latest VILLAScommon submodule 2020-06-11 14:20:33 +02:00
3b28eea7d2 aurora_axis: add two functions to reset counters and configure loopback mode 2020-06-11 13:08:42 +02:00
1596208bb6 aurora_axis: dump frame counters 2020-06-11 13:01:44 +02:00
3d15323376 aurora_axis: harmonize with HDL changes 2020-06-11 13:01:27 +02:00
bab9e22fdb update submodule urls 2020-06-11 12:37:53 +02:00
Hatim Kanchwala
448068082f Improve comments for status/control register bits 2020-06-08 00:55:33 +02:00
Hatim Kanchwala
0a7c6cc31c Define register addresses and bits 2020-06-05 23:41:08 +02:00
Hatim Kanchwala
4005a0b40e Merge branch 'master' of git.rwth-aachen.de:acs/public/villas/VILLASfpga 2020-06-02 00:54:54 +02:00
Hatim Kanchwala
bf67a2e5f0 Add initial Aurora driver 2020-06-02 00:54:31 +02:00
02f60eb86e add a writeMemory function to IpCore class 2020-05-26 15:24:15 +02:00
Hatim Kanchwala
73e85f2e5a Add intial header file for Aurora 2020-05-26 14:46:35 +02:00
dd1a17c4a5 update bitstream configs 2019-08-15 13:57:29 +02:00
44d63cd4b0 update common submodule 2019-08-15 13:57:17 +02:00
30dff972f2 several fixes for villas-fpga-pipe 2019-08-15 13:55:39 +02:00
f6a78bea69 dma: add dump() method 2019-08-15 13:54:58 +02:00
Hatim Kanchwala
bf74db8e79 Debug update 2019-06-24 12:11:44 -04:00
3326c83fc7 add note to cite our publication 2018-09-20 11:19:23 +02:00
5361c1d20d move gpu module to top level directory 2018-08-21 15:53:47 +02:00
3f119896e9 ci: some tweaks to fix unit-tests 2018-08-21 15:29:37 +02:00
d191a86c18 do not call copy-ctor of villas::HostRamAllocator 2018-08-21 14:25:42 +02:00
8b45a8bcac fix include paths 2018-08-21 14:25:20 +02:00
ea4b453250 tests: remove obsolete unit tests which have been moved to VILLAScommon 2018-08-21 13:54:21 +02:00
2112038d70 Merge branch 'feature/hls-rtds2gpu' into develop 2018-08-21 13:51:32 +02:00
5c7f167617 pipe: rename streamer to pipe (closes #19) 2018-08-21 13:40:38 +02:00
106d215dd2 fix gdrcopy submodule 2018-08-21 13:31:56 +02:00
4158ddb792 gpu: fix include paths and some linker settings 2018-08-21 13:28:07 +02:00
76b1695586 move more code to VILLAScommon repo 2018-08-21 13:27:04 +02:00
Daniel Krebs
96cd71a87e gpu/gdrcopy: rebase on current upstream master and update 2018-08-21 13:12:51 +02:00
5e8c602c8d ci: use Centos 7 based Docker Image with CUDA dev env from Nvidia 2018-08-21 12:39:39 +02:00